Intel Celeron D Processor 300 Sequence

Identification Information
Specification Update 13
Component Identification Information
The Intel® Celeron® D Processor on 65 nm process can be identified by the following
values:
Family
1
Model
2
1111b 0110b
NOTES:
1. The Family corresponds to bits [11:8] of the EDX register after RESET, bits [11:8] of
the EAX register after the CPUID instruction is executed with a 1 in the EAX register,
and the generation field of the Device ID register accessible through Boundary Scan.
2. The Model corresponds to bits [7:4] of the EDX register after RESET, bits [7:4] of the
EAX register after the CPUID instruction is executed with a 1 in the EAX register, and
the model field of the Device ID register accessible through Boundary Scan.
Cache and TLB descriptor parameters are provided in the EAX, EBX, ECX and EDX
registers after the CPUID instruction is executed with a 2 in the EAX register. Refer to
the Intel Processor Identification and the CPUID Instruction Application Note (AP-
485) and the Cedar Mill Processor Family BIOS Writer’s Guide (BWG) for further
information on the CPUID instruction.
Table 1. Intel
®
Celeron
®
D Processor 300 Sequence Identification Information
S-Spec
Core
Stepping
L2 Cache
Size
(bytes)
Processo
r
Signatur
e
Processo
r Number
Speed Core/Bus Package Notes
SL9XU C1 512K 0F64h 347
3.06 GHz/533
MHz
775-land LGA 1, 3, 4
SL96P C1 512K 0F64h 352
3.20 GHz/533
MHz
775-land LGA 1, 3, 4
SL96N C1 512K 0F64h 356
3.33 GHz/533
MHz
775-land LGA 1, 3, 4
SL9KK D0 512K 0F65h 360
3.46 GHz/533
MHz
775-land LGA 2, 3, 4
SL9KJ D0 512K 0F65h 365 3.6 GHz/533 MHz 775-land LGA 2, 3, 4
NOTES:
1. These processors support the 775_VR_CONFIG_05A (mainstream) specifications.
2. These processors support the 775_VR_CONFIG_06 specifications.
3. These parts support Intel® Extended Memory 64 Technology (Intel® EM64T).
4. These parts support Execute Disable Bit Feature.