Intel Celeron D Processor 300 Sequence

Errata
Specification Update 15
AD4. Incorrect Access Controls to MSR_LASTBRANCH_0_FROM_LIP MSR
Registers
Problem: When an access is made to the MSR_LASTBRANCH_0_FROM_LIP MSR register, an
expected #GP fault may not happen.
Implication: A read of the MSR_LASTBRANCH_0_FROM_LIP MSR register may not cause a #GP
fault.
Workaround: None identified
Status: For the steppings affected, see the Summary Tables of Changes.
AD5. FXRSTOR May Not Restore Non-canonical Effective Addresses on
Processors with Intel
®
Extended Memory 64 Technology (Intel
®
EM64T) Enabled
Problem: If an x87 data instruction has been executed with a non-canonical effective address,
FXSAVE may store that non-canonical FP Data Pointer (FDP) value into the save
image. An FXRSTOR instruction executed with 64-bit operand size may signal a
General Protection Fault (#GP) if the FDP or FP Instruction Pointer (FIP) is in non-
canonical form.
Implication: When this erratum occurs, Intel EM64T enabled systems may encounter an
unintended #GP fault.
Workaround: Software should avoid using non-canonical effective addressing in EM64T enabled
processors. BIOS can contain a workaround for this erratum removing
the unintended #GP fault on FXRSTOR.
Status: For the steppings affected, see the Summary Tables of Changes.
AD6. A Push of ESP That Faults May Zero the Upper 32 Bits of RSP
Problem: In the event that a push ESP instruction, that faults, is executed in compatibility
mode, the processor will incorrectly zero upper 32-bits of RSP.
Implication: A Push of ESP in compatibility mode will zero the upper 32-bits of RSP. Due to this
erratum, this instruction fault may change the contents of RSP. This erratum has not
been observed in commercially available software.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AD7. Checking of Page Table Base Address May Not Match the Address Bit
Width Supported by the Platform
Problem: If the page table base address, included in the page map level-4 table, page-
directory pointer table, page-directory table or page table, exceeds the physical
address range supported by the platform (e.g. 36-bit) and it is less than the
implemented address range (e.g. 40-bit), the processor does not check if the address
is invalid.