Intel Celeron D Processor 300 Sequence

Errata
16 Specification Update
Implication: If software sets such invalid physical address in those tables, the processor does not
generate a page fault (#PF) upon access to that virtual address, and the access
results in an incorrect read or write. If BIOS provides only valid physical address
ranges to the operating system, this erratum will not occur.
Workaround: BIOS must provide valid physical address ranges to the operating system.
Status: F006Fr the steppings affected, see the Summary Tables of Changes.
AD8. With TF (Trap Flag) Asserted, FP Instruction That Triggers an
Unmasked FP Exception May Take Single Step Trap before Retirement
of Instruction
Problem: If an FP instruction generates an unmasked exception with the EFLAGS.TF=1, it is
possible for external events to occur, including a transition to a lower power state.
When resuming from the lower power state, it may be possible to take the single
step trap before the execution of the original FP instruction completes.
Implication: A Single Step trap will be taken when not expected.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AD9. BTS (Branch Trace Store) and PEBS (Precise Event Based Sampling)
May Update Memory outside the BTS/PEBS Buffer
Problem: If the BTS/PEBS buffer is defined such that:
• The difference between BTS/PEBS buffer base and BTS/PEBS absolute maximum
is not an integer multiple of the corresponding record sizes
• BTS/PEBS absolute maximum is less than a record size from the end of the
virtual address space
• The record that would cross BTS/PEBS absolute maximum will also continue past
the end of the virtual address space
• A BTS/PEBS record can be written that will wrap at the 4G boundary (IA32) or
2^64 boundary (EM64T mode), and write memory outside of the BTS/PEBS
buffer.
Implication: Software that uses BTS/PEBS near the 4G boundary (IA32) or 2^64 boundary (Intel
EM64T mode), and defines the buffer such that it does not hold an integer multiple of
records can update memory outside the BTS/PEBS buffer.
Workaround: Define BTS/PEBS buffer such that BTS/PEBS absolute maximum minus BTS/PEBS
buffer base is integer multiple of the corresponding record sizes as recommended in
the IA-32 Intel
®
Architecture Software Developer’s Manual, Volume 3.
Status: For the steppings affected, see the Summary Tables of Changes.