Intel Celeron D Processor 300 Sequence

Errata
18 Specification Update
AD13. Two Correctable L2 Cache Errors in Close Proximity May Cause a
System Hang
Problem: If two correctable L2 cache errors are detected in close proximity to each other, a
livelock may occur as a result of the processor being unable to resolve this condition.
Implication: When this erratum occurs, the processor may livelock and result in a system hang.
Intel has only observed this erratum while injecting cache errors in simulation.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AD14. Processor May Hang with a 25% or Less STPCLK# Duty Cycle
Problem: If a system de-asserts STPCLK# at a 25% or less duty cycle and the processor
thermal control circuit (TCC) on-demand clock modulation is active, the processor
may hang. This erratum does not occur under the automatic mode of the TCC.
Implication: When this erratum occurs, the processor may hang.
Workaround: If use of the on-demand mode of the processor's TCC is desired in conjunction
with STPCLK# modulation, then assure that STPCLK# is not asserted at a 25% duty
cycle.
Status: For the steppings affected, see the Summary Tables of Changes.
AD15. Machine Check Exceptions May not Update Last-Exception Record
MSRs (LERs)
Problem: If a system de-asserts STPCLK# at a 25% or less duty cycle and the processor
thermal control circuit (TCC) on-demand clock modulation is active, the processor
may hang. This erratum does not occur under the automatic mode of the TCC.
Implication: When this erratum occurs, the LER may not contain information relating to the
machine check exception. They will contain information relating to the exception prior
to the machine check exception
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.