Intel Celeron D Processor 300 Sequence

Errata
Specification Update 19
AD16. Writing the Local Vector Table (LVT) when an Interrupt is Pending
May Cause an Unexpected Interrupt
Problem: If a local interrupt is pending when the LVT entry is written, an interrupt may be
taken on the new interrupt vector even if the mask bit is set.
Implication: An interrupt may immediately be generated with the new vector when a LVT entry is
written, even if the new LVT entry has the mask bit set. If there is no Interrupt
Service Routine (ISR) set up for that vector the system will GP fault. If the ISR does
not do an End of Interrupt (EOI) the bit for the vector will be left set in the in-service
register and mask all interrupts at the same or lower priority.
Workaround: Any vector programmed into an LVT entry must have an ISR associated with it,
even if that vector was programmed as masked. This ISR routine must do an EOI to
clear any unexpected interrupts that may occur. The ISR associated with
the spurious vector does not generate an EOI, therefore the spurious vector should
not be used when writing the LVT.
Status: For the steppings affected, see the Summary Tables of Changes.
AD17. At a Bus Ratio of 13:1, RCNT and Address Parity May be Incorrect
Problem: In a system running at the 13:1 bus ratio, RCNT[0] ( ADDR# [28], phase b) may
report incorrect information.
Implication: RCNT[0] may contain incorrect information and cause address parity machine check
errors.
Workaround: Address parity should be disabled and RCNT information should be ignored at the
bus ratio of 13:1.
Status: For the steppings affected, see the Summary Tables of Changes.
AD18. IRET under Certain Conditions May Cause an Unexpected Alignment
Check Exception
Problem: In IA-32e mode, it is possible to get an Alignment Check Exception (AC#) on the
IRET instruction even though alignment checks were disabled at the start of the
IRET. This can only occur if the IRET instruction is returning from CPL3 code to CPL3
code. IRETs from CPL0/1/2 are not affected. This erratum can occur if the EFLAGS
value on the stack has the AC flag set, and the interrupt handler's stack is
misaligned. In IA-32e mode, RSP is aligned to a 16-byte boundary before pushing
the stack frame.
Implication: In IA-32e mode, under the conditions given above, an IRET can get an AC# even if
alignment checks are disabled at the start of the IRET. This erratum can only be
observed with a software generated stack frame.
Workaround: Software should not generate misaligned stack frames for use with IRET.
Status: For the steppings affected, see the Summary Tables of Changes.