Intel Celeron D Processor 300 Sequence

Errata
20 Specification Update
AD19. L2 Cache ECC Machine Check Errors May be erroneously Reported
after an Asynchronous RESET# Assertion
Problem: Machine check status MSRs may incorrectly report the following L2 Cache ECC
machine-check errors when cache transactions are in-flight and RESET# is asserted:
• Instruction Fetch Errors (IA32_MC2_STATUS with MCA error code 153)
• L2 Data Write Errors (IA32_MC1_STATUS with MCA error code 145)
Implication: Uncorrected or corrected L2 ECC machine check errors may be erroneously reported.
Intel has not observed this erratum on any commercially available system.
Workaround: When a real run-time L2 Cache ECC Machine Check occurs, a corresponding valid
error will normally be logged in the IA32_MC0_STATUS register. BIOS may clear
IA32_MC2_STATUS and/or IA32_MC1_STATUS for these specific errors when
IA32_MC0_STATUS does not have its VAL flag set.
Status: For the steppings affected, see the Summary Tables of Changes.
AD20. Using 2M/4M Pages When A20M# Is Asserted May Result in
Incorrect Address Translations
Problem: An external A20M# pin if enabled forces address bit 20 to be masked (forced to zero)
to emulates real-address mode address wraparound at 1 megabyte. However, if all of
the following conditions are met, address bit 20 may not be masked:
• Paging is enabled.
• A linear address has bit 20 set.
• The address references a large page.
• A20M# is enabled.
Implication: When A20M# is enabled and an address references a large page the resulting
translated physical address may be incorrect. This erratum has not been observed
with any commercially available operating system.
Workaround: Operating systems should not allow A20M# to be enabled if the masking of
address bit 20 could be applied to an address that references a large page. A20M# is
normally only used with the first megabyte of memory.
Status: For the steppings affected, see the Summary Tables of Changes.