Intel Celeron D Processor 300 Sequence

Errata
Specification Update 21
AD21. Writing Shared Unaligned Data that Crosses a Cache Line without
Proper Semaphores or Barriers May Expose a Memory Ordering Issue
Problem: Software which is written so that multiple agents can modify the same shared
unaligned memory location at the same time may experience a memory ordering
issue if multiple loads access this shared data shortly thereafter. Exposure to this
problem requires the use of a data write which spans a cache line boundary.
Implication: This erratum may cause loads to be observed out of order. Intel has not observed
this erratum with any commercially available software or system.
Workaround: Software should ensure at least one of the following is true when modifying
shared data by multiple agents:
• The shared data is aligned
• Proper semaphores or barriers are used in order to prevent concurrent data
accesses
Status: For the steppings affected, see the Summary Tables of Changes.
AD22. The IA32_MC0_STATUS and IA32_MC1_STATUS Overflow Bit is not
set when Multiple Un-correctable Machine Check Errors Occur at the
Same Time
Problem: When two enabled MC0/MC1 un-correctable machine check errors are detected in the
same bank in the same internal clock cycle, the highest priority error will be logged in
IA32_MC0_STATUS / IA32_MC1_STATUS register, but the overflow bit may not be
set.
Implication: The highest priority error will be logged and signaled if enabled, but the overflow bit
in the IA32_MC0_STATUS/ IA32_MC1_STATUS register may not be set.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AD23. Processor May Fault When the Upper 8 Bytes of Segment Selector Is
Loaded from a Far Jump through a Call Gate via the Local Descriptor
Table
Problem: In IA-32e mode of the Intel EM64T processor, control transfers through a call gate
via the Local Descriptor Table (LDT) that uses a 16-byte descriptor, the upper 8-byte
access may wrap and access an incorrect descriptor in the LDT. This only occurs on
an LDT with a LIMIT>0x10008 with a 16-byte descriptor that has a selector of
0xFFFC.
Implication: In the event this erratum occurs, the upper 8-byte access may wrap and access an
incorrect descriptor within the LDT, potentially resulting in a fault or system hang.
Intel has not observed this erratum with any commercially available software.
Workaround: None identified.