Intel Celeron D Processor 300 Sequence

Errata
22 Specification Update
Status: For the steppings affected, see the Summary Tables of Changes.
AD24. The Processor May Issue Front Side Bus Transactions up to 6 Clocks
after RESET# Is Asserted
Problem: The processor may issue transactions beyond the documented 3 Front Side Bus
(FSB) clocks and up to 6 FSB clocks after RESET# is asserted in the case of a warm
reset. A warm reset is where the chipset asserts RESET# when the system is
running.
Implication: The processor may issue transactions up to 6 FSB clocks after the RESET# is
asserted
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AD25. Front Side Bus Machine Checks May be Reported as a Result of On-
Going Transactions during Warm Reset
Problem: Processor Front Side Bus (FSB) protocol/signal integrity machine checks may be
reported if the transactions are initiated or in-progress during a warm reset. A warm
reset is where the chipset asserts RESET# when the system is running.
Implication: The processor may log FSB protocol/signal integrity machine checks if transactions
are allowed to occur during RESET# assertions.
Workaround: BIOS may clear FSB protocol/signal integrity machine checks for
systems/chipsets which do not block new transactions during RESET# assertions.
Status: For the steppings affected, see the Summary Tables of Changes
AD26. A VM Exit Occuring in IA-32e Mode May Not Produce a VMX Abort
When Expected
Problem: If a VM exit occurs while the processor is in IA-32e mode and the “host address-
space size” VM-exit control is 0, a VMX abort should occur. Due to this erratum, the
expected VMX aborts may not occur and instead the VM Exit will occur normally. The
conditions required to observe this erratum are a VM entry that returns from SMM
with the “IA-32e guest” VM-entry control set to 1 in the SMM VMCS and the “host
address-space size” VM-exit control cleared to 0 in the executive VMCS.
Implication: A VM Exit will occur when a VMX Abort was expected.
Workaround: An SMM VMM should always set the “IA-32e guest” VM-entry control in the SMM
VMCS to be the value that was in the LMA bit (IA32_EFER.LMA.LMA[bit 10]) in the
IA32_EFER MSR (C0000080H) at the time of the last SMM VM exit. If this guideline is
followed, that value will be 1 only if the “host address-space size” VM-exit control is 1
in the executive VMCS.
Status: For the steppings affected, see the Summary Tables of Changes.