Intel Celeron D Processor 300 Sequence
Table Of Contents
- Contents
- Revision History
- 1 Introduction
- 2 Electrical Specifications
- 2.1 FSB and GTLREF
- 2.2 Power and Ground Lands
- 2.3 Decoupling Guidelines
- 2.4 Voltage Identification
- 2.5 Reserved, Unused, and TESTHI Signals
- 2.6 FSB Signal Groups
- 2.7 GTL+ Asynchronous Signals
- 2.8 Test Access Port (TAP) Connection
- 2.9 FSB Frequency Select Signals (BSEL[2:0])
- 2.10 Absolute Maximum and Minimum Ratings
- 2.11 Processor DC Specifications
- 2.12 VCC Overshoot Specification
- 2.13 GTL+ FSB Specifications
- 3 Package Mechanical Specifications
- 4 Land Listing and Signal Descriptions
- 5 Thermal Specifications and Design Considerations
- 6 Features
- 7 Boxed Processor Specifications
- 8 Debug Tools Specifications

Datasheet 3
Contents
1 Introduction.......................................................................................................................11
1.1 Terminology.........................................................................................................12
1.1.1 Processor Packaging Terminology.........................................................12
1.2 References..........................................................................................................13
2 Electrical Specifications....................................................................................................15
2.1 FSB and GTLREF ...............................................................................................15
2.2 Power and Ground Lands ...................................................................................15
2.3 Decoupling Guidelines ........................................................................................15
2.3.1 VCC Decoupling.....................................................................................16
2.3.2 FSB GTL+ Decoupling ...........................................................................16
2.3.3 FSB Clock (BCLK[1:0]) and Processor Clocking....................................16
2.4 Voltage Identification...........................................................................................17
2.4.1 Phase Lock Loop (PLL) Power and Filter...............................................19
2.5 Reserved, Unused, and TESTHI Signals............................................................20
2.6 FSB Signal Groups..............................................................................................20
2.7 GTL+ Asynchronous Signals...............................................................................22
2.8 Test Access Port (TAP) Connection....................................................................23
2.9 FSB Frequency Select Signals (BSEL[2:0]) ........................................................23
2.10 Absolute Maximum and Minimum Ratings..........................................................23
2.11 Processor DC Specifications...............................................................................24
2.11.1 Processor DC Specifications..................................................................24
2.12 VCC Overshoot Specification..............................................................................30
2.12.1 Die Voltage Validation............................................................................30
2.13 GTL+ FSB Specifications ....................................................................................31
3 Package Mechanical Specifications.................................................................................33
3.1 Package Mechanical Drawing .............................................................................33
3.2 Processor Component Keep-Out Zones .............................................................37
3.3 Package Loading Specifications .........................................................................37
3.4 Package Handling Guidelines .............................................................................37
3.5 Package Insertion Specifications ........................................................................38
3.6 Processor Mass Specification .............................................................................38
3.7 Processor Materials.............................................................................................38
3.8 Processor Markings.............................................................................................38
3.9 Processor Land Coordinates...............................................................................40
4 Land Listing and Signal Descriptions ...............................................................................41
4.1 Processor Land Assignments..............................................................................41
4.2 Alphabetical Signals Reference ..........................................................................62
5 Thermal Specifications and Design Considerations.........................................................71
5.1 Processor Thermal Specifications.......................................................................71
5.1.1 Thermal Specifications...........................................................................71
5.1.2 Thermal Metrology .................................................................................74
5.2 Processor Thermal Features...............................................................................74
5.2.1 Thermal Monitor .....................................................................................74