Intel Celeron D Processor 300 Sequence
Table Of Contents
- Contents
- Revision History
- 1 Introduction
- 2 Electrical Specifications
- 2.1 FSB and GTLREF
- 2.2 Power and Ground Lands
- 2.3 Decoupling Guidelines
- 2.4 Voltage Identification
- 2.5 Reserved, Unused, and TESTHI Signals
- 2.6 FSB Signal Groups
- 2.7 GTL+ Asynchronous Signals
- 2.8 Test Access Port (TAP) Connection
- 2.9 FSB Frequency Select Signals (BSEL[2:0])
- 2.10 Absolute Maximum and Minimum Ratings
- 2.11 Processor DC Specifications
- 2.12 VCC Overshoot Specification
- 2.13 GTL+ FSB Specifications
- 3 Package Mechanical Specifications
- 4 Land Listing and Signal Descriptions
- 5 Thermal Specifications and Design Considerations
- 6 Features
- 7 Boxed Processor Specifications
- 8 Debug Tools Specifications

Land Listing and Signal Descriptions
46 Datasheet
RESERVED AE4 — —
RESERVED AE6 — —
RESERVED AH2 — —
RESERVED C9 — —
RESERVED D1 — —
RESERVED D14 — —
RESERVED D16 — —
RESERVED E23 — —
RESERVED E24 — —
RESERVED E5 — —
RESERVED E6 — —
RESERVED E7 — —
RESERVED F23 — —
RESERVED F29 — —
RESERVED F6 — —
RESERVED G10 — —
RESERVED B13 — —
RESERVED J3 — —
RESERVED N4 — —
RESERVED N5 — —
RESERVED P5 — —
RESERVED Y3 — —
RESERVED D23 — —
RESERVED AK6 — —
RESERVED G6 — —
RESET# G23 Common Clock Input
RS0# B3 Common Clock Input
RS1# F5 Common Clock Input
RS2# A3 Common Clock Input
RSP# H4 Common Clock Input
SKTOCC# AE8 Power/Other Output
SMI# P2 Asynch GTL+ Input
STPCLK# M3 Asynch GTL+ Input
TCK AE1 TAP Input
TDI AD1 TAP Input
TDO AF1 TAP Output
TESTHI0 F26 Power/Other Input
TESTHI1 W3 Power/Other Input
TESTHI2 F25 Power/Other Input
TESTHI3 G25 Power/Other Input
TESTHI4 G27 Power/Other Input
TESTHI5 G26 Power/Other Input
TESTHI6 G24 Power/Other Input
TESTHI7 F24 Power/Other Input
Table 4-1. Alphabetical Land
Assignments
Land Name
Land
#
Signal Buffer
Type
Direction
TESTHI8 G3 Power/Other Input
TESTHI9 G4 Power/Other Input
TESTHI10 H5 Power/Other Input
TESTHI11 P1 Power/Other Input
TESTHI12 W2 Power/Other Input
TESTHI13 L2 Power/Other Input
THERMDA AL1 Power/Other —
THERMDC AK1 Power/Other —
THERMTRIP# M2 Asynch GTL+ Output
TMS AC1 TAP Input
TRDY# E3 Common Clock Input
TRST# AG1 TAP Input
VCC AA8 Power/Other —
VCC AB8 Power/Other —
VCC AC23 Power/Other —
VCC AC24 Power/Other —
VCC AC25 Power/Other —
VCC AC26 Power/Other —
VCC AC27 Power/Other —
VCC AC28 Power/Other —
VCC AC29 Power/Other —
VCC AC30 Power/Other —
VCC AC8 Power/Other —
VCC AD23 Power/Other —
VCC AD24 Power/Other —
VCC AD25 Power/Other —
VCC AD26 Power/Other —
VCC AD27 Power/Other —
VCC AD28 Power/Other —
VCC AD29 Power/Other —
VCC AD30 Power/Other —
VCC AD8 Power/Other —
VCC AE11 Power/Other —
VCC AE12 Power/Other —
VCC AE14 Power/Other —
VCC AE15 Power/Other —
VCC AE18 Power/Other —
VCC AE19 Power/Other —
VCC AE21 Power/Other —
VCC AE22 Power/Other —
VCC AE23 Power/Other —
VCC AE9 Power/Other —
VCC AF11 Power/Other —
VCC AF12 Power/Other —
Table 4-1. Alphabetical Land
Assignments
Land Name
Land
#
Signal Buffer
Type
Direction