Intel Celeron D Processor 300 Sequence

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Table Of Contents

Land Listing and Signal Descriptions

56 Datasheet

J30 VCC Power/Other —

K1 LINT0 Asynch GTL+ Input

K2 VSS Power/Other —

K3 A20M# Asynch GTL+ Input

K4 REQ0# Source Synch Input/Output

K5 VSS Power/Other —

K6 REQ3# Source Synch Input/Output

K7 VSS Power/Other —

K8 VCC Power/Other —

K23 VCC Power/Other —

K24 VCC Power/Other —

K25 VCC Power/Other —

K26 VCC Power/Other —

K27 VCC Power/Other —

K28 VCC Power/Other —

K29 VCC Power/Other —

K30 VCC Power/Other —

L1 LINT1 Asynch GTL+ Input

L2 TESTHI13 Power/Other Input

L3 VSS Power/Other —

L4 A6# Source Synch Input/Output

L5 A3# Source Synch Input/Output

L6 VSS Power/Other —

L7 VSS Power/Other —

L8 VCC Power/Other —

L23 VSS Power/Other —

L24 VSS Power/Other —

L25 VSS Power/Other —

L26 VSS Power/Other —

L27 VSS Power/Other —

L28 VSS Power/Other —

L29 VSS Power/Other —

L30 VSS Power/Other —

M1 VSS Power/Other —

M2 THERMTRIP# Asynch GTL+ Output

M3 STPCLK# Asynch GTL+ Input

M4 A7# Source Synch Input/Output

M5 A5# Source Synch Input/Output

M6 REQ2# Source Synch Input/Output

M7 VSS Power/Other —

M8 VCC Power/Other —

M23 VCC Power/Other —

M24 VCC Power/Other —

M25 VCC Power/Other —

Table 4-2. Numerical Land Assignments

Land

#

Land Name

Signal Buffer

Type

Direction

M26 VCC Power/Other —

M27 VCC Power/Other —

M28 VCC Power/Other —

M29 VCC Power/Other —

M30 VCC Power/Other —

N1 PWRGOOD Power/Other Input

N2 IGNNE# Asynch GTL+ Input

N3 VSS Power/Other —

N4 RESERVED — —

N5 RESERVED — —

N6 VSS Power/Other —

N7 VSS Power/Other —

N8 VCC Power/Other —

N23 VCC Power/Other —

N24 VCC Power/Other —

N25 VCC Power/Other —

N26 VCC Power/Other —

N27 VCC Power/Other —

N28 VCC Power/Other —

N29 VCC Power/Other —

N30 VCC Power/Other —

P1 TESTHI11 Power/Other Input

P2 SMI# Asynch GTL+ Input

P3 INIT# Asynch GTL+ Input

P4 VSS Power/Other —

P5 RESERVED — —

P6 A4# Source Synch Input/Output

P7 VSS Power/Other —

P8 VCC Power/Other —

P23 VSS Power/Other —

P24 VSS Power/Other —

P25 VSS Power/Other —

P26 VSS Power/Other —

P27 VSS Power/Other —

P28 VSS Power/Other —

P29 VSS Power/Other —

P30 VSS Power/Other —

R1 COMP3 Power/Other Input

R2 VSS Power/Other —

R3 FERR#/PBE# Asynch GTL+ Output

R4 A8# Source Synch Input/Output

R5 VSS Power/Other —

R6 ADSTB0# Source Synch Input/Output

R7 VSS Power/Other —

Table 4-2. Numerical Land Assignments

Land

#

Land Name

Signal Buffer

Type

Direction