Intel Celeron D Processor 300 Sequence
Table Of Contents
- Contents
- Revision History
- 1 Introduction
- 2 Electrical Specifications
- 2.1 FSB and GTLREF
- 2.2 Power and Ground Lands
- 2.3 Decoupling Guidelines
- 2.4 Voltage Identification
- 2.5 Reserved, Unused, and TESTHI Signals
- 2.6 FSB Signal Groups
- 2.7 GTL+ Asynchronous Signals
- 2.8 Test Access Port (TAP) Connection
- 2.9 FSB Frequency Select Signals (BSEL[2:0])
- 2.10 Absolute Maximum and Minimum Ratings
- 2.11 Processor DC Specifications
- 2.12 VCC Overshoot Specification
- 2.13 GTL+ FSB Specifications
- 3 Package Mechanical Specifications
- 4 Land Listing and Signal Descriptions
- 5 Thermal Specifications and Design Considerations
- 6 Features
- 7 Boxed Processor Specifications
- 8 Debug Tools Specifications

Land Listing and Signal Descriptions
58 Datasheet
Y30 VCC Power/Other —
AA1
VTT_OUT_
RIGHT
Power/Other Output
AA2 LL_ID1 Power/Other Output
AA3 VSS Power/Other —
AA4 A21# Source Synch Input/Output
AA5 A23# Source Synch Input/Output
AA6 VSS Power/Other —
AA7 VSS Power/Other —
AA8 VCC Power/Other —
AA23 VSS Power/Other —
AA24 VSS Power/Other —
AA25 VSS Power/Other —
AA26 VSS Power/Other —
AA27 VSS Power/Other —
AA28 VSS Power/Other —
AA29 VSS Power/Other —
AA30 VSS Power/Other —
AB1 VSS Power/Other —
AB2 IERR# Asynch GTL+ Output
AB3 MCERR# Common Clock Input/Output
AB4 A26# Source Synch Input/Output
AB5 A24# Source Synch Input/Output
AB6 A17# Source Synch Input/Output
AB7 VSS Power/Other —
AB8 VCC Power/Other —
AB23 VSS Power/Other —
AB24 VSS Power/Other —
AB25 VSS Power/Other —
AB26 VSS Power/Other —
AB27 VSS Power/Other —
AB28 VSS Power/Other —
AB29 VSS Power/Other —
AB30 VSS Power/Other —
AC1 TMS TAP Input
AC2 DBR# Power/Other Output
AC3 VSS Power/Other —
AC4 RESERVED — —
AC5 A25# Source Synch Input/Output
AC6 VSS Power/Other —
AC7 VSS Power/Other —
AC8 VCC Power/Other —
AC23 VCC Power/Other —
AC24 VCC Power/Other —
AC25 VCC Power/Other —
Table 4-2. Numerical Land Assignments
Land
#
Land Name
Signal Buffer
Type
Direction
AC26 VCC Power/Other —
AC27 VCC Power/Other —
AC28 VCC Power/Other —
AC29 VCC Power/Other —
AC30 VCC Power/Other —
AD1 TDI TAP Input
AD2 BPM2# Common Clock Input/Output
AD3 BINIT# Common Clock Input/Output
AD4 VSS Power/Other —
AD5 ADSTB1# Source Synch Input/Output
AD6 A22# Source Synch Input/Output
AD7 VSS Power/Other —
AD8 VCC Power/Other —
AD23 VCC Power/Other —
AD24 VCC Power/Other —
AD25 VCC Power/Other —
AD26 VCC Power/Other —
AD27 VCC Power/Other —
AD28 VCC Power/Other —
AD29 VCC Power/Other —
AD30 VCC Power/Other —
AE1 TCK TAP Input
AE2 VSS Power/Other —
AE3 RESERVED — —
AE4 RESERVED — —
AE5 VSS Power/Other —
AE6 RESERVED — —
AE7 VSS Power/Other —
AE8 SKTOCC# Power/Other Output
AE9 VCC Power/Other —
AE10 VSS Power/Other —
AE11 VCC Power/Other —
AE12 VCC Power/Other —
AE13 VSS Power/Other —
AE14 VCC Power/Other —
AE15 VCC Power/Other —
AE16 VSS Power/Other —
AE17 VSS Power/Other —
AE18 VCC Power/Other —
AE19 VCC Power/Other —
AE20 VSS Power/Other —
AE21 VCC Power/Other —
AE22 VCC Power/Other —
AE23 VCC Power/Other —
Table 4-2. Numerical Land Assignments
Land
#
Land Name
Signal Buffer
Type
Direction