Intel Celeron D Processor 300 Sequence
Table Of Contents
- Contents
- Revision History
- 1 Introduction
- 2 Electrical Specifications
- 2.1 FSB and GTLREF
- 2.2 Power and Ground Lands
- 2.3 Decoupling Guidelines
- 2.4 Voltage Identification
- 2.5 Reserved, Unused, and TESTHI Signals
- 2.6 FSB Signal Groups
- 2.7 GTL+ Asynchronous Signals
- 2.8 Test Access Port (TAP) Connection
- 2.9 FSB Frequency Select Signals (BSEL[2:0])
- 2.10 Absolute Maximum and Minimum Ratings
- 2.11 Processor DC Specifications
- 2.12 VCC Overshoot Specification
- 2.13 GTL+ FSB Specifications
- 3 Package Mechanical Specifications
- 4 Land Listing and Signal Descriptions
- 5 Thermal Specifications and Design Considerations
- 6 Features
- 7 Boxed Processor Specifications
- 8 Debug Tools Specifications

Land Listing and Signal Descriptions
Datasheet 59
AE24 VSS Power/Other —
AE25 VSS Power/Other —
AE26 VSS Power/Other —
AE27 VSS Power/Other —
AE28 VSS Power/Other —
AE29 VSS Power/Other —
AE30 VSS Power/Other —
AF1 TDO TAP Output
AF2 BPM4# Common Clock Input/Output
AF3 VSS Power/Other —
AF4 A28# Source Synch Input/Output
AF5 A27# Source Synch Input/Output
AF6 VSS Power/Other —
AF7 VSS Power/Other —
AF8 VCC Power/Other —
AF9 VCC Power/Other —
AF10 VSS Power/Other —
AF11 VCC Power/Other —
AF12 VCC Power/Other —
AF13 VSS Power/Other —
AF14 VCC Power/Other —
AF15 VCC Power/Other —
AF16 VSS Power/Other —
AF17 VSS Power/Other —
AF18 VCC Power/Other —
AF19 VCC Power/Other —
AF20 VSS Power/Other —
AF21 VCC Power/Other —
AF22 VCC Power/Other —
AF23 VSS Power/Other —
AF24 VSS Power/Other —
AF25 VSS Power/Other —
AF26 VSS Power/Other —
AF27 VSS Power/Other —
AF28 VSS Power/Other —
AF29 VSS Power/Other —
AF30 VSS Power/Other —
AG1 TRST# TAP Input
AG2 BPM3# Common Clock Input/Output
AG3 BPM5# Common Clock Input/Output
AG4 A30# Source Synch Input/Output
AG5 A31# Source Synch Input/Output
AG6 A29# Source Synch Input/Output
AG7 VSS Power/Other —
Table 4-2. Numerical Land Assignments
Land
#
Land Name
Signal Buffer
Type
Direction
AG8 VCC Power/Other —
AG9 VCC Power/Other —
AG10 VSS Power/Other —
AG11 VCC Power/Other —
AG12 VCC Power/Other —
AG13 VSS Power/Other —
AG14 VCC Power/Other —
AG15 VCC Power/Other —
AG16 VSS Power/Other —
AG17 VSS Power/Other —
AG18 VCC Power/Other —
AG19 VCC Power/Other —
AG20 VSS Power/Other —
AG21 VCC Power/Other —
AG22 VCC Power/Other —
AG23 VSS Power/Other —
AG24 VSS Power/Other —
AG25 VCC Power/Other —
AG26 VCC Power/Other —
AG27 VCC Power/Other —
AG28 VCC Power/Other —
AG29 VCC Power/Other —
AG30 VCC Power/Other —
AH1 VSS Power/Other —
AH2 RESERVED — —
AH3 VSS Power/Other —
AH4 A32# Source Synch Input/Output
AH5 A33# Source Synch Input/Output
AH6 VSS Power/Other —
AH7 VSS Power/Other —
AH8 VCC Power/Other —
AH9 VCC Power/Other —
AH10 VSS Power/Other —
AH11 VCC Power/Other —
AH12 VCC Power/Other —
AH13 VSS Power/Other —
AH14 VCC Power/Other —
AH15 VCC Power/Other —
AH16 VSS Power/Other —
AH17 VSS Power/Other —
AH18 VCC Power/Other —
AH19 VCC Power/Other —
AH20 VSS Power/Other —
AH21 VCC Power/Other —
Table 4-2. Numerical Land Assignments
Land
#
Land Name
Signal Buffer
Type
Direction