Intel Celeron D Processor 300 Sequence

80 Datasheet
Features
6.2.1 Normal State
This is the normal operating state for the processor.
6.2.2 HALT Powerdown State
HALT is a low power state entered when all the logical processors have executed the HALT or
MWAIT instructions. When one of the logical processors executes the HALT instruction, that
logical processor is halted; however, the other processor continues normal operation. The processor
will transition to the Normal state upon the occurrence of SMI#, BINIT#, INIT#, or LINT[1:0]
(NMI, INTR). RESET# will cause the processor to immediately initialize itself.
The return from a System Management Interrupt (SMI) handler can be to either Normal Mode or
the HALT Power Down state. See the Intel Architecture Software Developer's Manual, Volume III:
System Programmer's Guide for more information.
The system can generate a STPCLK# while the processor is in the HALT Power Down state. When
the system de-asserts the STPCLK# interrupt, the processor will return execution to the HALT
state.
While in HALT Power Down state, the processor will process bus snoops.
Figure 6-1. Processor Low Power State Machine
HALT State
BCLK running
Snoops and interrupts allow ed
Nor m al State
Normal execution
HALT Snoop State
BCLK running
Service snoops to caches
Stop-Grant State
BCLK running
Snoops and interrupts allow ed
Snoop
Event
Occurs
Snoop
Event
Serviced
INIT#, BINIT#, INTR, NMI, SMI#,
RESET#, FSB interrupts
STPCLK#
Asserted
STPCLK#
De-as serted
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Snoop Event Occurs
Snoop Event Serviced
HALT or MWAIT Instruction and
HALT Bus Cycle Generated
Grant Snoop State
BCLK running
Service snoops to caches