Intel Celeron D Processor 300 Sequence

Datasheet 81
Features
6.2.3 Stop-Grant States
When the STPCLK# signal is asserted, the Stop-Grant state of the processor is entered 20 bus
clocks after the response phase of the processor-issued Stop Grant Acknowledge special bus cycle.
Since the GTL+ signals receive power from the FSB, these signals should not be driven (allowing
the level to return to V
TT
) for minimum power drawn by the termination resistors in this state. In
addition, all other input signals on the FSB should be driven to the inactive state.
BINIT# will not be serviced while the processor is in Stop-Grant state. The event will be latched
and can be serviced by software upon exit from the Stop Grant state.
RESET# will cause the processor to immediately initialize itself, but the processor will stay in
Stop-Grant state. A transition back to the Normal state will occur with the de-assertion of the
STPCLK# signal.
A transition to the HALT/Grant Snoop state will occur when the processor detects a snoop on the
FSB (see Section 6.2.4).
While in the Stop-Grant state, SMI#, INIT#, BINIT# and LINT[1:0] will be latched by the
processor, and only serviced when the processor returns to the Normal state. Only one occurrence
of each event will be recognized upon return to the Normal state.
While in Stop-Grant state, the processor will process a FSB snoop.
6.2.4 HALT Snoop State, Grant Snoop State
The processor will respond to snoop transactions on the FSB while in Stop-Grant state or in HALT
Power Down state. During a snoop transaction, the processor enters the HALT:Grant Snoop state.
The processor will stay in this state until the snoop on the FSB has been serviced (whether by the
processor or another agent on the FSB). After the snoop is serviced, the processor will return to the
Stop-Grant state or HALT Power Down state, as appropriate.
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