Intel Celeron D Processor 300 Sequence
Table Of Contents
- Contents
- Revision History
- 1 Introduction
- 2 Electrical Specifications
- 2.1 FSB and GTLREF
- 2.2 Power and Ground Lands
- 2.3 Decoupling Guidelines
- 2.4 Voltage Identification
- 2.5 Reserved, Unused, and TESTHI Signals
- 2.6 FSB Signal Groups
- 2.7 GTL+ Asynchronous Signals
- 2.8 Test Access Port (TAP) Connection
- 2.9 FSB Frequency Select Signals (BSEL[2:0])
- 2.10 Absolute Maximum and Minimum Ratings
- 2.11 Processor DC Specifications
- 2.12 VCC Overshoot Specification
- 2.13 GTL+ FSB Specifications
- 3 Package Mechanical Specifications
- 4 Land Listing and Signal Descriptions
- 5 Thermal Specifications and Design Considerations
- 6 Features
- 7 Boxed Processor Specifications
- 8 Debug Tools Specifications
Datasheet 9
Intel
®
Celeron
®
D Processor 300 Sequence
Features
The Intel
®
Celeron
®
D processor family expands Intel’s processor family into the value-priced PC
market segment. Celeron D processors provide the value that offers the customer the capability to
affordably get onto the Internet, and use educational programs, home-office software, and
productivity applications. All of the Celeron D processors include an integrated L2 cache, and are
built on Intel’s advanced CMOS process technology. The Celeron D processor is backed by over
30 years of Intel experience in manufacturing high-quality, reliable microprocessors.
Intel
®
Extended Memory 64 Technology (Intel
®
EM64T) enables Celeron D processors to execute
operating systems and applications written to take advantage of the Intel EM64T.
The Celeron D processor also includes the Execute Disable Bit capability. This feature, combined
with a supported operating system, allows memory to be marked as executable or non-executable.
§
Available at 3.33 GHz, 3.20 GHz,
3.06 GHz, 2.93 GHz, 2.80 GHz, 2.66 GHz,
and 2.53 GHz
Binary compatible with applications
running on previous members of the Intel
microprocessor line
FSB frequencies at 533 MHz
Hyper-Pipelined Technology
—Advance Dynamic Execution
—Very deep out-of-order execution
Enhanced branch prediction
Optimized for 32-bit applications running
on advanced 32-bit operating systems
775-Land Package
16-KB Level 1 data cache
256-KB Advanced Transfer Cache (on-die,
full-speed Level 2 (L2) cache) with 4-way
associativity and Error Correcting Code
(ECC)
144 Streaming SIMD Extensions 2 (SSE2)
instructions
Supports Execute Disable Bit capability
13 Streaming SIMD Extensions 3 (SSE3)
instructions
Power Management capabilities
—System Management mode
—Multiple low-power states