Intel Celeron D Processor 300 Sequence
Table Of Contents
- Contents
- Revision History
- 1 Introduction
- 2 Electrical Specifications
- 2.1 FSB and GTLREF
- 2.2 Power and Ground Lands
- 2.3 Decoupling Guidelines
- 2.4 Voltage Identification
- 2.5 Reserved, Unused, and TESTHI Signals
- 2.6 FSB Signal Groups
- 2.7 GTL+ Asynchronous Signals
- 2.8 Test Access Port (TAP) Connection
- 2.9 FSB Frequency Select Signals (BSEL[2:0])
- 2.10 Absolute Maximum and Minimum Ratings
- 2.11 Processor DC Specifications
- 2.12 VCC Overshoot Specification
- 2.13 GTL+ FSB Specifications
- 3 Package Mechanical Specifications
- 4 Land Listing and Signal Descriptions
- 5 Thermal Specifications and Design Considerations
- 6 Features
- 7 Boxed Processor Specifications
- 8 Debug Tools Specifications

Datasheet 93
Debug Tools Specifications
8 Debug Tools Specifications
Refer to the ITP700 Debug Port Design Guide for information regarding debug tools
specifications. The ITP700 Debug Port Design Guide is located on http://developer.intel.com.
8.1 Logic Analyzer Interface (LAI)
Intel is working with two logic analyzer vendors to provide logic analyzer interfaces (LAIs) for use
in debugging Celeron D processor in the 775-land package systems. Tektronix* and Agilent*
should be contacted to get specific information about their logic analyzer interfaces. The following
information is general in nature. Specific information must be obtained from the logic analyzer
vendor.
Due to the complexity of Celeron D processor in the 775-land package systems, the LAI is critical
in providing the ability to probe and capture FSB signals. There are two sets of considerations to
keep in mind when designing a Celeron D processor in the 775-land package system that can make
use of an LAI: mechanical and electrical.
8.1.1 Mechanical Considerations
The LAI is installed between the processor socket and the Celeron D processor in the 775-land
package. The LAI lands plug into the socket, while the Celeron D processor in the 775-land
package lands plug into a socket on the LAI. Cabling that is part of the LAI egresses the system to
allow an electrical connection between the Celeron D processor in the 775-land package and a
logic analyzer. The maximum volume occupied by the LAI, known as the keep-out volume, as well
as the cable egress restrictions, should be obtained from the logic analyzer vendor. System
designers must make sure that the keep-out volume remains unobstructed inside the system. Note
that it is possible that the keep-out volume reserved for the LAI may differ from the space normally
occupied by the Celeron D processor in the 775-land package heatsink. If this is the case, the logic
analyzer vendor will provide a cooling solution as part of the LAI.
8.1.2 Electrical Considerations
The LAI will also affect the electrical performance of the FSB; therefore, it is critical to obtain
electrical load models from each of the logic analyzers to be able to run system level simulations to
prove that their tool will work in the system. Contact the logic analyzer vendor for electrical
specifications and load models for the LAI solution they provide.
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