Guide

I/O Subsystem
R
182 Intel
®
852GM Chipset Platform Design Guide
10.9.1. ICH4-M – LAN Connect Interface Guidelines
This Section contains guidelines on how to implement a Platform LAN Connect device on a system
motherboard. It should not be treated as a specification and the system designer must ensure through
simulations or other techniques that the system meets the specified timings. Special care must be given
to matching the LAN_CLK traces to those of the other signals, as shown below. The following signal
lines are used on this interface and are guidelines for the ICH4-M to LAN Connect Interface.
• LAN_CLK
• LAN_RSTSYNC
• LAN_RXD[2:0]
• LAN_TXD[2:0]
This interface supports Intel 82562ET and Intel 82562EM components. Signal lines LAN_CLK,
LAN_RSTSYNC, LAN_RXD[0], and LAN_TXD[0] are shared by all components.
10.9.1.1. Bus Topologies
The Platform LAN Connect Interface can be configured in several topologies:
• Direct point-to-point connection between the ICH4-M and the LAN component
• LOM Implementation
10.9.1.1.1. LOM (LAN On Motherboard) Point-To-Point Interconnect
The following are guidelines for a single solution motherboard. Either Intel 82562EM or Intel 82562ET
is uniquely installed.
Figure 96. Single Solution Interconnect
ICH4-M
Platform
LAN
Connect
(PLC)
LAN_CLK
LAN_RSTSYNC
LAN_RXD[2:0]
LAN_TXD[2:0]
L