Guide

ManualsBrandsIntel ManualsOtherIntel Celeron Processor 1.40 GHz, 256K Cache, 100 MHz FSB

Mobile Intel Pentium 4 Processor–M and Mobile Intel Celeron Processor FSB Design Guidelines

Intel

852GM Chipset Platform Design Guide 39

4.3.3. Common Clock (CC) AGTL+ Signal Group

Common clock signals should be routed to a minimum pin-to-pin motherboard length of 0.5 inches and

a maximum motherboard length of 6.5 inches.

Table 4. Processor Front Side Bus Control Signal Routing Guidelines

Signal Names

Routing Trace Length

(Pin-to-Pin)

CPU GMCH

Topology

Max

(inches)

Min

(inches)

Nominal Impedance

(ohms)

Width & Spacing

(mils)

RESET# CPURST# Stripline 6.5 0.5 55 ± 15% 4 & 8

BR0# BREQ0# Stripline 6.5 0.5 55 ± 15% 4 & 8

BNR# BNR# Stripline 6.5 0.5 55 ± 15% 4 & 8

REQ[4:0]# HREQ[4:0]# Stripline 6.5 0.5 55 ± 15% 4 & 8

BPRI# BPRI# Stripline 6.5 0.5 55 ± 15% 4 & 8

DEFER# DEFER# Stripline 6.5 0.5 55 ± 15% 4 & 8

LOCK# HLOCK# Stripline 6.5 0.5 55 ± 15% 4 & 8

TRDY# HTRDY# Stripline 6.5 0.5 55 ± 15% 4 & 8

DRDY# DRDY# Stripline 6.5 0.5 55 ± 15% 4 & 8

ADS# ADS# Stripline 6.5 0.5 55 ± 15% 4 & 8

DBSY# DBSY# Stripline 6.5 0.5 55 ± 15% 4 & 8

HIT# HIT# Stripline 6.5 0.5 55 ± 15% 4 & 8

HITM# HITM# Stripline 6.5 0.5 55 ± 15% 4 & 8

RS[2:0]# RS[2:0]# Stripline 6.5 0.5 55 ± 15% 4 & 8

NOTES:

1. Trace width of 4 mils and trace spacing of 8 mils within signal groups. Entire trace for each signal routed on one

layer (recommended)

2. RESET# and BR0# are common clock AGTL+ signals without ODT (On die termination). These signals require

an external Rtt. The Rtt should be placed near CPU: L2<= 0.5 inches. Rtt = 51.1 ±1%.

4.3.4. Asynchronous AGTL+ Signals

All signals must meet the AC and DC specifications as documented in the Mobile Intel

Pentium

Processor–M Datasheet.

4.3.4.1. Topology 1A: Open Drain (OD) Signals Driven by the Processor – IERR#

and FERR#

The Topology 1A OD signals IERR# and FERR# should adhere to the following routing and layout

recommendations. Table 5 lists the recommended routing requirements for the IERR# and FERR#

signals of the Mobile Intel Pentium 4 Processor–M. The routing guidelines allow the signal to be routed