Design Guide

R
10 Intel
®
855GM/855GME Chipset Platform Design Guide
13.5.2.5.
DDR SMRCOMP and VTT 1.25-V Supply Disable in
S3/Suspend .................................................................................. 269
13.5.3. Other GMCH Reference Voltage and Analog Power Delivery .................... 269
13.5.3.1. GMCH GTLVREF ......................................................................... 269
13.5.3.2. GMCH AGTL+ I/O Buffer Compensation ..................................... 270
13.5.3.3. GMCH AGTL+ Reference Voltage ............................................... 271
13.5.3.4. GMCH Analog Power ................................................................... 271
13.5.4. ICH4-M Decoupling / Power Delivery Guidelines........................................ 272
13.5.4.1. ICH4-M Decoupling ...................................................................... 272
13.5.5. Hub Interface Decoupling ............................................................................ 273
13.5.6. FWH Decoupling.......................................................................................... 273
13.5.7. General LAN Decoupling............................................................................. 273
14. Intel Pro/Wireless 2100/2100A – Bluetooth Coexistence Interface Design Requirements ..... 275
14.1. PCB Interface Requirements ...................................................................................... 275
14.2. DC Power Requirements for Bluetooth....................................................................... 276
14.3. Start Up Conditions and Logic Protection ................................................................... 276
14.4. USB Selective Suspend .............................................................................................. 277
15. Reserved, NC, and Test Signals.............................................................................................. 279
15.1. Intel Pentium M Processor and Intel Celeron M Processor RSVD Signals ................ 279
15.2. Intel Pentium M Processor on 90 nm Process with 2 MB L2 Cache
Processor RSVD Signals ............................................................................................ 279
15.3. Intel 855GM/GME Chipset GMCH RSVD Signals ...................................................... 280
16. Platform Design Checklist ........................................................................................................ 281
16.1. General Information..................................................................................................... 281
16.2. Customer Implementation of Voltage Rails................................................................. 282
16.3. Design Checklist Implementation................................................................................ 282
16.4. Intel Pentium M Processor / Intel Celeron M Processor ............................................. 284
16.4.1. Resistor Recommendations ........................................................................ 284
16.4.2. In Target Probe (ITP)................................................................................... 287
16.4.3. Decoupling Recommendations.................................................................... 287
16.4.3.1. VCCP (I/O).................................................................................... 287
16.4.3.2. VCCA (PLL) .................................................................................. 288
16.4.3.3. VCC (CORE) ................................................................................ 288
16.5. CK-408 Clock Checklist............................................................................................... 289
16.5.1. Resistor Recommendations ........................................................................ 289
16.6. Intel 855GM/855GME Checklist................................................................................. 291
16.6.1. System Memory........................................................................................... 291
16.6.1.1. GMCH System Memory Interface ................................................ 291
16.6.1.2. DDR SO-DIMM Interface.............................................................. 293
16.6.1.3. SODIMM Decoupling Recommendation ...................................... 293
16.6.2. FSB .............................................................................................................. 294
16.6.3. Hub Interface ............................................................................................... 295
16.6.4. Graphics Interfaces...................................................................................... 295
16.6.4.1. LVDS .................................................................................... 295
16.6.4.2. DVO .................................................................................... 296
16.6.4.3. DAC .................................................................................... 297
16.6.5. Miscellaneous .............................................................................................. 298
16.6.6. GMCH Decoupling Recommendations ....................................................... 299
16.7. ICH4-M Checklist ........................................................................................................ 301
16.7.1. PCI Interface and Interrupts ........................................................................ 301
16.7.2. GPIO ............................................................................................................ 302