Design Guide

System Memory Design Guidelines (DDR-SDRAM) for SO-DIMM configuration
R
102 Intel
®
855GM/855GME Chipset Platform Design Guide
6.3.6.5. Command Topology 2 Routing Guidelines
Table 33. Command Topology 2 Routing Guidelines
Parameter Routing Guidelines
Signal Group SMA[12:6,3,0], SBA[1:0], SRAS#, SCAS#, SWE#
Motherboard Topology Branched T with Parallel Termination
Reference Plane Ground Referenced
Characteristic Trace Impedance (Zo) 55 Ω ± 15%
Nominal Trace Width
Inner layers: 4 mils
Outer layers: 5 mils
Minimum Spacing to Trace Width Ratio 2 to 1 (e.g. 8 mil space to 4 mil trace)
Minimum Isolation Spacing to non-DDR Signals 20 mils
Package Length P1
500 mils +/- 250 mils
(See Table 35 for exact package length.)
Stub Length S0, S1 Max = 0.25”
Trace Length L2 – Series Resistor Pad to First SO-DIMM
Pad
Max = 1.0 inches
Total Length L1+ S0 + L2 – Total length from GMCH ball
to First SO-DIMM pad
Min = 0.5”
Max = 5.0”
Total Length L1+ L3 + S1 – Total length from GMCH ball
to Second SO-DIMM pad
Min = 1.0”
Max = 7.0”
Total Length S0 + L2 + L3 + S1– Total SO-DIMM pad to
SO-DIMM pad spacing
Max = 3.0”
Trace Length L4 – Second SO-DIMM Via to Parallel
Resistor Pad
Max = 1.5”
Series Termination Resistor (Rs) 10 Ω ± 5%
Parallel Termination Resistor (Rt) 56 Ω ± 5%
Maximum Recommended Motherboard Via Count Per
Signal
6
Length Matching Requirements
CMD to SCK/SCK# [5:0]
See length matching Section 6.3.6.6 and Figure 46 for
details.
NOTES:
1. Recommended resistor values and trace lengths may change in a later revision of the design guide.
2. Power distribution vias from Rt to Vtt are not included in this count.
3. The overall maximum and minimum length to the SO-DIMM must comply with clock length matching
requirements.
4. It is possible to route using 3 vias if one via is shared that connects to the SO-DIMM0 pad and series
termination resistor, if a via is shared that connects L1 to series termination and if one via is shared that
connects to the SO-DIMM1 pad and parallel termination resistor.