Design Guide

R
12 Intel
®
855GM/855GME Chipset Platform Design Guide
Figures
Figure 1. Intel Pentium M Processor and Intel 855GM Chipset Block Diagram...................... 26
Figure 2. Intel Pentium M, Intel Pentium M Processor on 90 nm Process with 2 MB L2 Cache,
Intel Celeron M Processor and 855GME Chipset System Block Diagram ..............30
Figure 3. Recommended Board Stack-Up Dimensions........................................................... 34
Figure 4. Trace Spacing vs. Trace to Reference Plane Example............................................ 38
Figure 5. Three to One Trace Spacing to Trace Width Example............................................. 38
Figure 6. Common Clock Topology ......................................................................................... 40
Figure 7. Layer 6 PSB Source Synchronous Signals GND Referencing to Layer 5 ............... 42
Figure 8. Layer 3 PSB Source Synchronous Signals .............................................................. 43
Figure 9. Routing Illustration for Topology 1A .........................................................................50
Figure 10. Routing Illustration for Topology 1B .......................................................................51
Figure 11. Routing Illustration for Topology 1C .......................................................................52
Figure 12. Routing Illustration for Topology 2A .......................................................................52
Figure 13. Routing Illustration for Topology 2B .......................................................................53
Figure 14. Routing Illustration for Topology 2C .......................................................................54
Figure 15. Routing Illustration for Topology 3..........................................................................54
Figure 16. Voltage Translation Circuit...................................................................................... 55
Figure 17. Processor RESET# Signal Routing Topology with NO ITP700FLEX Connector... 56
Figure 18. Processor RESET# Signal Routing Topology with ITP700FLEX Connector .........56
Figure 19. Processor RESET# Signal Routing Example with ITP700FLEX Debug Port ........ 57
Figure 20. Processor and GMCH Host Clock Layout Routing Example .................................58
Figure 21. Processor GTLREF Voltage Divider Network ........................................................59
Figure 22. Processor GTLREF Motherboard Layout............................................................... 60
Figure 23. Processor COMP[2] & COMP[0] Resistive Compensation .................................... 61
Figure 24. Processor COMP[3] & COMP[1] Resistive Compensation .................................... 61
Figure 25. Processor COMP[3:0] Resistor Layout...................................................................62
Figure 26. Processor COMP[1:0] Resistor Alternative Primary Side Layout........................... 62
Figure 27. COMP2 & COMP0 27.4-Ω Traces..........................................................................63
Figure 28. V
CCSENSE
/V
SSSENSE
Routing Example .......................................................................64
Figure 29. ITP700FLEX Debug Port Signals ........................................................................... 67
Figure 30. ITP700FLEX Signals Layout Example ...................................................................71
Figure 31. ITP_CLK to ITP700FLEX Connector Layout Example........................................... 71
Figure 32. ITP_CLK to CPU ITP Interposer Layout Example.................................................. 73
Figure 33. Memory Clock Routing Topology SCK/SCK#[5:0] .................................................79
Figure 34. Memory Clock Trace Length Matching Diagram .................................................... 81
Figure 35. Clock Signal Routing Example ............................................................................... 83
Figure 36. Data Signal Routing Topology................................................................................ 84
Figure 37. SDQS to Clock Trace Length Matching Diagram...................................................87
Figure 38. SDQ/SDM to SDQS Trace Length Matching Diagram ........................................... 89
Figure 39. Data Signals Group Routing Example.................................................................... 91
Figure 40. Control Signal Routing Topology............................................................................ 92
Figure 41. Control Signal to Clock Trace Length Matching Diagram ...................................... 95
Figure 42. Control Signals Group Routing Example................................................................ 96
Figure 43. Command Routing for Topology 1.......................................................................... 98
Figure 44. Topology 1 Command Signal to Clock Trace Length Matching Diagram ............ 100
Figure 45. Command Routing Topology 2............................................................................. 101
Figure 46. Topology 2 Command Signal to Clock Trace Length Matching Diagram ............ 104
Figure 47. Example of Command Signal Group .................................................................... 105
Figure 48. Command Routing Topology 3............................................................................. 106
Figure 49. Topology 3 Command Signal to Clock Trace Length Matching Diagram ............ 109