Design Guide

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Intel® 855GM/855GME Chipset Platform Design Guide 13
Figure 50. Command per Clock Signal Routing Topology .................................................... 112
Figure 51. CPC Signals to Clock Length Matching Diagram ................................................ 114
Figure 52. DDR Memory Thermal Sensor Placement........................................................... 118
Figure 53. Recommended Device Order for Micro-DIMM/Memory Down Combination...... 120
Figure 54. DDR Clock Routing to Micro-DIMM .................................................................... 123
Figure 55. DDR Clock Routing to Memory Down Two Load BGA ........................................ 124
Figure 56. DDR Clock Routing to Memory Down Two Load TSOP...................................... 124
Figure 57. DDR Clock Routing to Memory Down 4 Load BGA............................................. 124
Figure 58. DDR Clock Trace Length Matching Diagram....................................................... 128
Figure 59. Data Signal Routing GMCH to 1x16 TSOP/BGA & /1x8 BGA Configuration ...... 131
Figure 60. Data Signal Routing GMCH to 2x16 BGA Configuration ..................................... 131
Figure 61. SDQS to Clock Trace Length Matching Diagram ................................................ 134
Figure 62. SDQ/SDM to SDQS Trace Length Matching Diagram ........................................ 136
Figure 63. Control Signal Routing GMCH to Micro-DIMM Pad ............................................. 140
Figure 64. Control Signal Routing GMCH to Memory Down 1x16 4 Load TSOP................. 140
Figure 65. Control Signal Routing GMCH to Memory Down 1x16/2x16 4 Load BGA .......... 141
Figure 66. Control Signal Routing GMCH to Memory Down 1x8 8 Loads BGA ................... 141
Figure 67. Control Signal to Clock Trace Length Matching Diagram.................................... 144
Figure 68. CMD Signal Routing GMCH to Micro-DIMM and Mem Down TSOP 4 Load ...... 146
Figure 69. CMD Signal Routing GMCH to Micro-DIMM and Mem Down BGA 4 Load......... 146
Figure 70. CMD Signal Routing GMCH to Micro-DIMM and Memory Down BGA 8-Load ... 147
Figure 71. Topology 1 Command Signal to Clock Trace Length Matching Diagram........... 150
Figure 72. Command Per Clock Signal Routing Topology 4 Load BGA............................... 153
Figure 73. CPC Signal Routing Topology 4 Load TSOP ...................................................... 153
Figure 74. CPC Signal Routing 8 Load BGA Topology......................................................... 154
Figure 75. CPC Signal Routing Micro-DIMM......................................................................... 154
Figure 76. CPC Signals to Clock Length Matching Diagram ................................................ 157
Figure 77. Refset Placement ................................................................................................. 160
Figure 78. GMCH DAC Routing Guidelines with Docking Connector................................... 161
Figure 79. DAC R, G, B Routing and Resistor Layout example............................................ 163
Figure 80. DVOB and DVOC Simulations Model .................................................................. 172
Figure 81. Driver-Receiver Waveforms Relationship Specification ...................................... 172
Figure 82. DVO Enabled Simulation Model........................................................................... 173
Figure 83. Generic Module Connector Parasitic Model ........................................................ 174
Figure 84. GVREF Reference Voltage .................................................................................. 176
Figure 85. AGP Layout Guidelines........................................................................................ 180
Figure 86. DPMS Circuit........................................................................................................ 186
Figure 87. Hub Interface Routing Example ........................................................................... 187
Figure 88. Single VREF/VSWING Voltage Generation Circuit for Hub Interface ................. 191
Figure 89. ICH4-M and GMCH Locally Generated Reference Voltage Divider Circuit......... 192
Figure 90. Shared GMCH & ICH4-M Reference Voltage with Separate Voltage Divider Circuit
for VSWING and VREF.......................................................................................... 192
Figure 91. Individual HIVREF and HI_VSWING Voltage Reference Divider Circuits for ICH4-M
and GMCH ............................................................................................................. 193
Figure 92. Connection Requirements for Primary IDE Connector ........................................ 196
Figure 93. Connection Requirements for Secondary IDE Connector ................................... 197
Figure 94. PCI Bus Layout Example ..................................................................................... 200
Figure 95. Intel 82801DBM ICH4-M AC’97 – Codec Connection ......................................... 201
Figure 96. Intel 82801DBM ICH4-M AC’97 – AC_BIT_CLK Topology ................................. 202
Figure 97. Intel 82801DBM AC’97 – AC_SDOUT/AC_SYNC Topology............................... 202
Figure 98. Intel 82801DBM AC’97 – AC_SDIN Topology ..................................................... 203
Figure 99. Example Speaker Circuit...................................................................................... 206
Figure 100. Recommended USB Trace Spacing .................................................................. 207