Design Guide

System Memory Design Guidelines (DDR-SDRAM) for Memory Down Configuration
R
Intel
®
855GM/855GME Chipset Platform Design Guide 131
7.3.4.1. Data Bus Topology
Figure 59. Data Signal Routing GMCH to 1x16 TSOP/BGA & /1x8 BGA Configuration
Figure 60. Data Signal Routing GMCH to 2x16 BGA Configuration
The data signals should be routed using a 2 to 1 trace spacing to trace width ratio for signals within the
DDR group, except clocks and strobes. There should be a minimum of 20 mils of spacing to non-DDR
related signals. Data signals should be routed on inner layers with minimized external trace lengths.