Design Guide

R
14 Intel
®
855GM/855GME Chipset Platform Design Guide
Figure 101. USBRBIAS Connection ......................................................................................208
Figure 102. Good Downstream Power Connection ...............................................................210
Figure 103. Common Mode Choke Schematic...................................................................... 210
Figure 104. SMBUS 2.0/SMLink Protocol..............................................................................213
Figure 105. High Power/Low Power Mixed V
CC
_
SUSPEND
/V
CC
_
CORE
Architecture ................... 214
Figure 106. FWH VPP Isolation Circuitry...............................................................................217
Figure 107. RTCX1 and SUSCLK Relationship in ICH4-M ...................................................218
Figure 108. External Circuitry for the ICH4-M Where the Internal RTC is Not Used............. 218
Figure 109. External Circuitry for the ICH4-M RTC ...............................................................219
Figure 110. Diode Circuit to Connect RTC External Battery .................................................222
Figure 111. RTCRST# External Circuit for the ICH4-M RTC ................................................222
Figure 112. Intel 82801DBM ICH4-M/Platform LAN Connect Section ..................................224
Figure 113. Single Solution Interconnect............................................................................... 226
Figure 114. LAN_CLK Routing Example ............................................................................... 227
Figure 115. Intel 82562ET / Intel 82562EM Termination .......................................................228
Figure 116. Critical Dimensions for Component Placement..................................................229
Figure 117. Termination Plane............................................................................................... 231
Figure 118. Intel 82562ET/EM Disable and Power Down Circuitry .......................................231
Figure 119. Trace Routing ..................................................................................................... 233
Figure 120. Ground Plane Separation ................................................................................... 235
Figure 121. ICH4-M CPU I/O Signals with Processor and FWH ........................................... 238
Figure 122. Clock Distribution Diagram ................................................................................. 240
Figure 123. Source Shunt Termination Topology ..................................................................241
Figure 124. BCLK to GCLKIN Timing Requirement ..............................................................244
Figure 125. CLK66 Clock Group Topology............................................................................ 245
Figure 126. CLK33 Group Topology ...................................................................................... 247
Figure 127. PCI Clock Group Topology................................................................................. 248
Figure 128. CLK14 Clock Group Topology............................................................................ 249
Figure 129. DOTCLK Clock Topology ................................................................................... 250
Figure 130. SSCCLK Clock Topology.................................................................................... 251
Figure 131. USBCLK Clock Topology.................................................................................... 252
Figure 132. Platform Power Delivery Map ............................................................................. 256
Figure 133. GMCH Power-Up Sequence ..............................................................................259
Figure 134. ICH4-M Power-Up Sequence ............................................................................. 260
Figure 135. Example V
5REF
/ V
5REFSUS
Sequencing Circuitry .................................................. 262
Figure 136. V5REFSUS With +V5ALWAYS Connection Option ...........................................262
Figure 137. V5REFSUS With +V3ALWAYS and +V5S or +V5 Connection Option .............. 263
Figure 138. Example for Minimizing Loop Inductance...........................................................264
Figure 139. DDR Power Delivery Block Diagram .................................................................. 267
Figure 140. GMCH SMRCOMP Resistive Compensation.....................................................268
Figure 141. GMCH System Memory Reference Voltage Generation Circuit ........................268
Figure 142. GMCH HDVREF[2:0] Reference Voltage Generation Circuit............................. 269
Figure 143. GMCH HAVREF Reference Voltage Generation Circuit.................................... 270
Figure 144. GMCH HCCVREF Reference Voltage Generation Circuit ................................. 270
Figure 145. GMCH HXRCOMP and HYRCOMP Resistive Compensation........................... 270
Figure 146. GMCH HXSWING and HYSWING Reference Voltage Generation Circuit........271
Figure 147. Example Analog Supply Filter............................................................................. 271
Figure 148. Recommended Topology for Coexistence Traces ............................................. 276
Figure 149. Routing Illustration for INIT# ............................................................................... 286
Figure 150. Voltage Translation Circuit for PROCHOT# .......................................................286
Figure 151. Clock Power-down Implementation ....................................................................290
Figure 152. Reference Voltage Level for SMVREF ............................................................... 293
Figure 153. GMCH HXSWING & HYSWING Reference Voltage Generation Circuit............294