Manualshelf

Design Guide

ManualsBrandsIntel ManualsOtherIntel Celeron Processor 1.40 GHz, 256K Cache, 100 MHz FSB
141142143144145146147148149150
System Memory Design Guidelines (DDR-SDRAM) for Memory Down Configuration
R
Intel
®
855GM/855GME Chipset Platform Design Guide 141
Figure 65. Control Signal Routing GMCH to Memory Down 1x16/2x16 4 Load BGA
Figure 66. Control Signal Routing GMCH to Memory Down 1x8 8 Loads BGA
The control signals should be routed using 2 to 1 trace spacing to trace width ratio for signals within the
DDR group, except clocks and strobes. There should be a minimum of 20-mils of spacing to non-DDR
related signals. Control signals should be routed on inner layers with minimized external trace lengths.