Design Guide

System Memory Design Guidelines (DDR-SDRAM) for Memory Down Configuration
R
142 Intel
®
855GM/855GME Chipset Platform Design Guide
7.3.5.2. Control Signal Routing Guidelines
Table 50. Control Signal Routing Guidelines
Parameter Routing Guidelines
Signal Group SCKE[3:0], SCS#[3:0]
Motherboard Topology Point-to-Point with Parallel Termination
Reference Plane Ground Referenced
Characteristic Trace Impedance (Zo) 55 Ω ± 15%
Nominal Trace Width
Inner layers: 4 mils
Outer layers: 5 mils
Minimum Spacing to Trace Width Ratio 2 to 1 (e.g. 8 mil space to 4 mil trace)
Minimum Isolation Spacing to non-DDR Signals 20 mils
Package Length P1
500 mils +/- 250 mils
(see Table 51 for exact package lengths.)
Stub Length S1 Max = 250 mils
Trace Length L1 – GMCH Control Signal Ball to Micro-DIMM
pad
Min = 0.25 inches
Max = 4 inches
Trace Length L2 – Micro-DIMM Pad to Parallel Termination
Resistor Pad
Max = 2 inches
TL0
Min = 0.5 inches
Max = 1.5 inches
TL1
Min = 0.3 inches
Max = 0.7 inches
TL2
Min = 100 mils Max = 500 mils (see Figure 64)
Min = 0.3 in Max = 0.7 in (see Figure 65)
Min = 0.3 in Max = 0.7 in (see Figure 66)
TL3
Min = 100 mils Max = 500 mils (see Figure 65)
Min = 0.3 in Max = 0.7 in (see Figure 66)
TL4 Min = 100 mils Max = 500 mils
Parallel Termination Resistor (Rt) 56 Ω ± 5%
Maximum Recommended Motherboard Via Count Per Signal 7
Length Matching Requirements
CTRL to SCK/SCK# [4,3,1,0]
See length matching Section 7.3.5.3 and Figure 67.
NOTE: The overall maximum and minimum length to the Micro-DIMM must comply with clock length matching
requirements.