Design Guide

System Memory Design Guidelines (DDR-SDRAM) for Memory Down Configuration
R
148 Intel
®
855GM/855GME Chipset Platform Design Guide
7.3.6.2. Command Topology Routing Guidelines
Table 52. Command Topology 1 Routing Guidelines
Parameter Routing Guidelines
Signal Group SMA[12:6,3,0], SBA[1:0], SRAS#, SCAS#, SWE#
Motherboard Topology Daisy Chain with Parallel Termination
Reference Plane Ground Referenced
Characteristic Trace Impedance (Zo) 55 Ω ± 15%
Nominal Trace Width
Inner layers: 4 mils
Outer layers: 5 mils
Minimum Spacing to Trace Width Ratio 2 to 1 (e.g. 8 mil space to 4 mil trace)
Minimum Isolation Spacing to non-DDR Signals 20 mils
Package Length P1
500 mils +/- 250 mils
(see Table 53 for exact package lengths.)
Stub Length S1 Max = 0.25 inches
Stub Length S2 Max = 0.25 inches
Trace Length L1
Min = 0.5 inch
Max = 4.0 inches
Trace Length L2 Max = 1.0 inches
Trace Length L3 Max = 1.0 inches
Trace Length TL0
Min = 0.5 inches
Max = 1.5 inches
Trace Length TL1 Max = 0.5 inches
Trace Length TL2 Max = 0.5 inches
Trace Length TL3
Min = 0.4 inches
Max = 0.8 inches
Trace Length TL4 Max = 0.5 inches
Series Termination Resistor (Rs) 10 Ω ± 5%
Parallel Termination Resistor (Rt) 56 Ω ± 5%
Maximum Recommended Motherboard Via Count Per
Signal
18
Length Matching Requirements
CMD to SCK/SCK# [5:0]
See length matching Section 7.3.6.3 and Figure 71 for details.
NOTES:
1. Recommended resistor values and trace lengths may change in a later revision of the design guide.
2. Power distribution vias from Rt to Vtt are not included in this count.
3. The overall maximum and minimum length to the Micro-DIMM and Memory Down must comply with clock length
matching requirements.