Design Guide

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Intel® 855GM/855GME Chipset Platform Design Guide 15
Figure 154. DPMS Clock Implementation ............................................................................. 297
Figure 155. Single or Locally Generated GMCH and ICH4-M HIVREF/HI_VSWING Circuit 307
Figure 156. Single Generated GMCH and ICH4-M VSWING/VREF Reference Voltage/ Local
Voltage Divider Circuit for VSWING/VREF............................................................ 307
Figure 157. External Circuitry for the RTC ............................................................................ 308
Figure 158. Good Downstream Power Connection............................................................... 312
Figure 159. LAN_RST# Design Recommendation ............................................................... 313