Design Guide

System Memory Design Guidelines (DDR-SDRAM) for Memory Down Configuration
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154 Intel
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855GM/855GME Chipset Platform Design Guide
Figure 74. CPC Signal Routing 8 Load BGA Topology
Figure 75. CPC Signal Routing Micro-DIMM
The CPC signals should be routed using 2 to 1 trace space to width ratio for signals within the DDR
group, except clocks and strobes. There should be a minimum of 20-mils of spacing to non-DDR related
signals. CPC signals should be routed on inner layers with minimized external trace lengths.