Design Guide

System Memory Design Guidelines (DDR-SDRAM) for Memory Down Configuration
R
156 Intel
®
855GM/855GME Chipset Platform Design Guide
7.3.7.3. CPC to Clock Length Matching Requirements
The total length of the CPC signals, between the GMCH die pad and the Micro-DIMM/Memory Down
device must fall within the range defined below, with respect to the associated clock reference length.
Refer to Figure 72, Figure 73, Figure 74, and Figure 75 for a definition of the various trace segments.
The trace length from the Micro-DIMM to the termination resistor does not need to be length matched.
The length matching requirements are also depicted in Figure 76. Refer to Section 7.1 for more details
on length matching requirements. A table of CPC signal package length is provided in Section 7.3.7.4.
Length range formula for Micro-DIMM:
X
0
= SCK/SCK#[1:0] total reference length, including package length. See Section 7.3.3.1
Y
0
= SMA[5,4,2,1] total length = P1 + L1+ S1, see Figure 72
where: ( X
0
– 1.0” ) ≤ Y
0
≤ ( X
0
+ 0.5” )
Length range formula for Memory Down:
X
1
= SCK/SCK#[4:3] total reference length, including package length. See Section 7.3.3.1.
Y
1
= SMAB[5,4,2,1] total length = P1 + L1 + TL0 + TL1 + TL2, see Figure 73
= SMAB[5,4,2,1] total length = P1 + L1 + TL0 + TL1 + TL2 + TL3, see Figure 74, and Figure 75
= SMAB[5,4,2,1] total length = P1 + L1 + TL0 + TL1 + TL3, see Figure 74, and Figure 75
where: ( X
1
– 1.0” ) ≤ Y
1
≤ ( X
1
+ 0.5” )
No length matching is required to the termination resistor. Figure 76on the following page depicts the
length matching requirements between the CPC signals and clock. A nominal CPC package length of
500 mils can be used to estimate baseline MB lengths. Refer to Section 7.2 for more details on package
length compensation.