Design Guide

R
16 Intel
®
855GM/855GME Chipset Platform Design Guide
Tables
Table 1. Conventions and Terminology ................................................................................... 21
Table 2. Processor System Bus Common Clock Signal Internal Layer Routing Guidelines... 39
Table 3. Processor and GMCH PSB Common Clock Signal Package Lengths and Minimum
Board Trace Lengths................................................................................................ 40
Table 4. Processor PSB Data Source Synchronous Signal Trace Length Mismatch Mapping44
Table 5. Processor System Bus Source Synchronous Data Signal Routing Guidelines ........45
Table 6. Processor PSB Address Source Synchronous Signal Trace Length Mismatch
Mapping.................................................................................................................... 45
Table 7. Processor PSB Source Synchronous Address Signal Routing Guidelines............... 46
Table 8. Intel Pentium M / Intel Celeron M Processor and GMCH Source Synchronous FSB
Signal Package Lengths........................................................................................... 47
Table 9. Asynchronous AGTL+ Nets .......................................................................................49
Table 10. Layout Recommendations for Topology 1A............................................................. 50
Table 11. Layout Recommendations for Topology 1B............................................................. 51
Table 12. Layout Recommendations for Topology 1C ............................................................ 52
Table 13. Layout Recommendations for Topology 2A............................................................. 53
Table 14. Layout Recommendations for Topology 2B............................................................. 53
Table 15. Layout Recommendations for Topology 2C ............................................................ 54
Table 16. Layout Recommendations for Topology 3 ...............................................................55
Table 17. Processor RESET# Signal Routing Guidelines with ITP700FLEX Connector ........57
Table 18. ITP Signal Default Strapping When ITP Debug Port Not Used ............................... 64
Table 19. Recommended ITP700FLEX Signal Terminations.................................................. 69
Table 20. GMCH Chipset Memory Signal Groups................................................................... 76
Table 21. Intel 855GM Chipset GMCH DDR 200/266 Length Matching Formulas ................. 77
Table 22. Intel 855GME Chipset GMCH DDR 200/266/333 Length Matching Formulas........ 77
Table 23. Clock Signal Mapping ..............................................................................................78
Table 24. Clock Signal Group Routing Guidelines ..................................................................79
Table 25. Memory Clock Package Lengths ............................................................................. 82
Table 26. Memory Data Signal Group Routing Guidelines......................................................85
Table 27. SDQ/SDM to SDQS Mapping .................................................................................. 88
Table 28. Memory SDQ/SDM/SDQS Package Lengths ..........................................................89
Table 29. Control Signal to SO-DIMM Mapping ......................................................................92
Table 30. Control Signal Routing Guidelines........................................................................... 93
Table 31. Control Group Package Lengths .............................................................................97
Table 32. Command Topology 1 Routing Guidelines ..............................................................98
Table 33. Command Topology 2 Routing Guidelines ............................................................102
Table 34. Command Topology 3 Routing Guidelines ............................................................107
Table 35. Command Group Package Lengths ......................................................................110
Table 36. CPC Signal to SO-DIMM Mapping ........................................................................111
Table 37. CPC Signal Routing Guidelines............................................................................. 112
Table 38. CPC Group Package Lengths ...............................................................................114
Table 39. Supported Memory Configurations - Micro-DIMM ................................................. 120
Table 40. Supported Memory Configurations - Memory Down .............................................121
Table 41. Montara-GM GMCH Chipset DDR Signal Groups................................................. 121
Table 42. Length Matching Formulas .................................................................................... 122
Table 43. Clock Signal Mapping ............................................................................................123
Table 44. Clock Signal Group Routing Guidelines ................................................................125
Table 45. DDR Clock Package Lengths ................................................................................129