Design Guide

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Intel® 855GM/855GME Chipset Platform Design Guide 17
Table 46. Data Signal Group Routing Guidelines ................................................................. 132
Table 47. SDQ/SDM to SDQS Mapping................................................................................ 135
Table 48. DDR SDQ/SDM/SDQS Package Lengths............................................................. 137
Table 49. Control Signal to Micro-DIMM/Memory Down Mapping........................................ 139
Table 50. Control Signal Routing Guidelines ........................................................................ 142
Table 51. Control Group Package Lengths........................................................................... 144
Table 52. Command Topology 1 Routing Guidelines ........................................................... 148
Table 53. Command Group Package Lengths...................................................................... 151
Table 54. CPC Signal to SO-DIMM Micro-Dimm and/or Memory Down Mapping................ 152
Table 55. CPC Signal Routing Guidelines ............................................................................ 155
Table 56. CPC Group Package Lengths ............................................................................... 157
Table 57. Recommended GMCH DAC Components............................................................ 162
Table 58. Signal Group and Signal Pair Names ................................................................... 165
Table 59. LVDS Signal Group Routing Guidelines ............................................................... 166
Table 60. LVDS Package Lengths ........................................................................................ 167
Table 61. DVO Interface Signal Groups................................................................................ 168
Table 62. DVO Interface Trace Length Mismatch Requirements ......................................... 169
Table 63. DVOB and DVOC Routing Guideline Summary.................................................... 170
Table 64. DVO Interface Package Lengths........................................................................... 171
Table 65. Allowable Interconnect Skew Calculation ............................................................. 172
Table 66. DVO Enabled Routing Guideline Summary .......................................................... 173
Table 67. GMBUS Pair Mapping and Options....................................................................... 174
Table 68. AGP 2.0 Signal Groups ......................................................................................... 178
Table 69. AGP 2.0 Data/Strobe Associations ....................................................................... 178
Table 70. Layout Routing Guidelines for AGP 1X Signals .................................................... 179
Table 71. Layout Routing Guidelines for AGP 2X/4X Signals............................................... 181
Table 72. AGP 2.0 Data Lengths Relative to Strobe Length................................................. 181
Table 73. AGP 2.0 Routing Guideline Summary................................................................... 182
Table 74. AGP Interface Package Length............................................................................. 183
Table 75. AGP Pull-Up/Pull-Down Requirements and Straps .............................................. 185
Table 76. AGP 2.0 Pull-up Resistor Values .......................................................................... 185
Table 77. Hub Interface RCOMP Resistor Values ................................................................ 187
Table 78. Hub Interface Signals Internal Layer Routing Summary....................................... 188
Table 79. Hub Interface Package Lengths for ICH4-M ......................................................... 189
Table 80. Hub Interface Package Lengths for GMCH........................................................... 189
Table 81. Hub Interface VREF/VSWING Reference Voltage Specifications ........................ 190
Table 82. Recommended Resistor Values for Single VREF/VSWING Divider Circuit ......... 191
Table 83. Recommended Resistor Values for Separate HIVREF and HI_VSWING Divider
Circuits ................................................................................................................... 192
Table 84. Recommended Resistor Values for HIVREF and HI_VSWING Divider Circuits for
ICH4-M................................................................................................................... 193
Table 85. AC’97 AC_BIT_CLK Routing Summary ................................................................ 202
Table 86. AC’97 AC_SDOUT/AC_SYNC Routing Summary ................................................ 203
Table 87. AC’97 AC_SDIN Routing Summary ...................................................................... 203
Table 88. Supported Codec Configurations .......................................................................... 205
Table 89. USBRBIAS/USBRBIAS# Routing Summary ......................................................... 208
Table 90. USB 2.0 Trace Length Guidelines (With Common-mode Choke) ........................ 208
Table 91. Bus Capacitance Reference Chart........................................................................ 215
Table 92. Bus Capacitance/Pull-Up Resistor Relationship ................................................... 215
Table 93. RTC Routing Summary ......................................................................................... 219
Table 94. LAN Component Connections/Features ............................................................... 224
Table 95. LAN Design Guide Section Reference.................................................................. 225
Table 96. LAN LOM Routing Summary................................................................................. 226