Design Guide

R
18 Intel
®
855GM/855GME Chipset Platform Design Guide
Table 97. Intel 82562ET/EM Control Signals.........................................................................232
Table 98. Individual Clock Breakdown...................................................................................239
Table 99. Host Clock Group Routing Constraints.................................................................. 242
Table 100. Clock Package Length ......................................................................................... 243
Table 101. CLK66 Clock Group Routing Constraints ............................................................246
Table 102. CLK33 Clock Group Routing Constraints ............................................................247
Table 103. PCICLK Clock Group Routing Constraints ..........................................................248
Table 104. CLK14 Clock Group Routing Constraints ............................................................249
Table 105. DOTCLK Clock Routing Constraints.................................................................... 250
Table 106. SSCCLK Clock Routing Constraints.................................................................... 251
Table 107. USBCLK Clock Routing Constraints.................................................................... 252
Table 108. Power Delivery Definitions ...................................................................................255
Table 109. Power Management States on Intel Reference Board ........................................257
Table 110. Power Supply Rail Descriptions on Intel Reference Board ................................. 257
Table 111. Timing Sequence Parameters ICH4-M................................................................261
Table 112. DDR Power-Up Initialization Sequence ............................................................... 263
Table 113. GMCH Decoupling Recommendations................................................................265
Table 114. Analog Supply Filter Requirements .....................................................................272
Table 115. ICH4-M Decoupling Requirements ...................................................................... 273
Table 116. Processor RSVD and TEST Signal Pin-Map Locations ......................................279
Table 117. Intel 855GM/GME Chipset GMCH RSVD and NC Signal Pin-Map Locations ....280