Design Guide

I/O Subsystem
R
196 Intel
®
855GM/855GME Chipset Platform Design Guide
11.1.2. Primary IDE Connector Requirements
Figure 92. Connection Requirements for Primary IDE Connector
Intel
®
ICH4-M
Primary IDE Connector
PCIRST#
†
PDD[15:0]
PDA[2:0]
PDCS[3,1]#
PDIOR#
PDDREQ
PDDACK#
PDIOW#
PIORDY (PRDSTB / PWDMARDY#)
4.7K
8.2~10K
3.3V
3.3V
PDIAG# / CBLID#
IRQ[14]
GPIOx
CSEL
10K
Ω
†
Due to ringing,
PCIRST# must be
buffered
22 to 47
Follow these connection requirements for Primary IDE connector:
• 22 Ω - 47 Ω series resistors are required on RESET#. The correct value should be determined for
each unique motherboard design, based on signal quality.
• An 8.2 kΩ - 10 kΩ pull-up resistor is required on IRQ14 to VCC3_3.
• A 4.7-kΩ, pull-up resistor to VCC3_3 is required on PIORDY and SIORDY.
• Series resistors can be placed on the control and data lines to improve signal quality. The resistors
are placed as close to the connector as possible. Values are determined for each unique
motherboard design.
• The 10-kΩ resistor to ground on the PDIAG#/CBLID# signal is required on the Primary
Connector. This change is to prevent the GPI pin from floating if a device is not present on the
IDE interface.