Design Guide

I/O Subsystem
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212 Intel
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855GM/855GME Chipset Platform Design Guide
11.5. I/O APIC (I/O Advanced Programmable Interrupt
Controller)
The Intel ICH4-M is designed to be backwards compatible with a number of the legacy interrupt
handling mechanisms as well as to be compliant with the latest I/O (x) APIC architecture. In addition to
implementing two 8259 interrupt controllers (PIC), the ICH4-M also incorporates an Advanced
Programmable Interrupt Controller (APIC) that is implemented via the 3-wire serial APIC bus that
connects all I/O and local APICs. An advancement in the interrupt delivery and control architecture of
the ICH4-M is represented by support for the I/O (x) APIC specification where PCI devices deliver
interrupts as write cycles that are written directly to a register that represents the desired interrupt. These
are ultimately delivered via the serial APIC bus or FSB. Furthermore, on Intel Pentium M processor /
Intel Celeron M based systems, the ICH4-M has the option to let the integrated I/O APIC behave as an
I/O (x) APIC. This allows the ICH4-M to deliver interrupts in a parallel manner rather than just a serial
one. This is accomplished by I/O APIC writes to a region of memory that is snooped by the processor
and thereby knows what interrupt goes active.
On Intel Pentium M / Intel Celeron M processor-based platforms, the serial I/O APIC bus interface of
the ICH4-M should be disabled. I/O (x) APIC is supported on the platform and the servicing of
interrupts is accomplished via a PSB interrupt delivery mechanism.
The serial I/O APIC bus interface of the ICH4-M should be disabled as follows.
• Tie APICCLK directly to ground.
• Tie APICD0, APICD1 to ground through a 10-kΩ resistor. (Separate pull-downs are required if
using XOR chain testing)
The Intel Pentium M processor and Intel Celeron M processor do not have pins dedicated for a serial I/O
APIC bus interface and thus, no hardware change is necessary. However, it is strongly encouraged to
enable I/O APIC support in the BIOS and operating system on Intel Pentium M processor / Intel Celeron
M based systems rather than the legacy 8259 interrupt controller due to the performance benefits and
efficiencies that the I/O (x) APIC architecture enjoys over the older PIC architecture.
11.6. SMBus 2.0/SMLink Interface
The SMBus interface on the ICH4-M uses two signals SMBCLK and SMBDATA to send and receive
data from components residing on the bus. These signals are used exclusively by the SMBus Host
Controller. The SMBus Host Controller resides inside the ICH4-M.
The ICH4-M incorporates an SMLink interface supporting Alert-on-LAN*, Alert-on-LAN2*, and a
slave functionality. It uses two signals SMLINK[1:0]. SMLINK[0] corresponds to an SMBus clock
signal and SMLINK[1] corresponds to an SMBus data signal. These signals are part of the SMB Slave
Interface.
For Alert-on-LAN* functionality, the ICH4-M transmits heartbeat and event messages over the
interface. When using the Intel 82562EM Platform LAN Connect Component, the ICH4-M’s integrated
LAN Controller will claim the SMLink heartbeat and event messages and send them out over the
network. An external, Alert-on-LAN2*-enabled LAN Controller (i.e. Intel 82562EM 10/100 Mbps
Platform LAN Connect) will connect to the SMLink signals to receive heartbeat and event messages, as
well as access the ICH4-M SMBus Slave Interface. The slave interface function allows an external