Design Guide

I/O Subsystem
R
214 Intel
®
855GM/855GME Chipset Platform Design Guide
11.6.1. SMBus Architecture and Design Considerations
11.6.1.1. SMBus Design Considerations
There is not a single SMBus design solution that will work for all platforms. One must consider the total
bus capacitance and device capabilities when designing SMBus segments. Routing SMBus to the PCI
slots makes the design process even more challenging since they add so much capacitance to the bus.
This extra capacitance has a large affect on the bus time constant which in turn affects the bus rise and
fall times.
Primary considerations in the design process are:
1. Device class (High/Low power). Most designs use primarily High Power Devices.
2. Are there devices that must run in S3?
3. Amount of V
CC
_
SUSPEND
current available, i.e. minimizing load of V
CC
_
SUSPEND.
11.6.1.2. General Design Issues/Notes
Regardless of the architecture used, there are some general considerations.
1. The pull-up resistor size for the SMBus data and clock signals is dependent on the bus load (this
includes all device leakage currents). Generally the SMBus device that can sink the least amount
of current is the limiting agent on how small the resistor can be. The pull-up resistor cannot be
made so large that the bus time constant (Resistance X Capacitance) does not meet the SMBus
rise and fall time specification.
2. The maximum bus capacitance that a physical segment can reach is 400 pF.
3. The Intel ICH4-M does not run SMBus cycles while in S3.
4. SMBus devices that can operate in S3 must be powered by the V
CC
_
SUSPEND
supply.
11.6.1.3. High Power/Low Power Mixed Architecture
This design allows for current isolation of high and low current devices while also allowing SMBus
devices to communicate during the S3 state. V
CC
_
SUSPEND
leakage is minimized by keeping non-essential
devices on the core supply. This is accomplished by the use of a “FET” to isolate the devices powered
by the core and suspend supplies. See Figure 105.
Figure 105. High Power/Low Power Mixed V
CC
_
SUSPEND
/V
CC
_
CORE
Architecture
ICH4
High
Current
Low
Current
VccSusVccSus3_3
Vcc
SMBus
Devices running in Standby
-
Non- Standby devices
Vcc
VccSus VccSus3_3
SMBus
Vcc
SMBus
Devices running in Standby
Non
-Standby devices
Vcc
Current Isolation
Logic
Buffered Power Good Signal From
Power Supply
Buffered Power Good Signal From
Power Supply