Design Guide

I/O Subsystem
R
226 Intel
®
855GM/855GME Chipset Platform Design Guide
11.9.2.1. Bus Topologies
The Platform LAN Connect Interface can be configured in several topologies:
• Direct point-to-point connection between the ICH4-M and the LAN component
• LOM Implementation
11.9.2.1.1. LAN On Motherboard Point-To-Point Interconnect
The following are guidelines for a single solution motherboard. Either Intel 82562EM or Intel 82562ET
is uniquely installed.
Figure 113. Single Solution Interconnect
Intel
®
ICH4-M
Platform
LAN
Connect
(PLC)
LAN_CLK
LAN_RSTSYNC
LAN_RXD[2:0]
LAN_TXD[2:0]
L
Table 96. LAN LOM Routing Summary
Trace Impedance LAN Routing
Requirements
Maximum Trace
Length
Signal
Referencing
LAN Signal Length Matching
55Ω ± 15%
5 on 10 4.5 to 12 inches Ground Data signals must be equal to
or no more than 0.5 inches
(500 mils) shorter than the
LAN clock trace.
11.9.2.2. Signal Routing and Layout
Platform LAN Connect Interface signals must be carefully routed on the motherboard to meet the timing
and signal quality requirements of this interface specification. The following are some general
guidelines that should be followed. Intel recommends that the board designer simulate the board routing
to verify that the specifications are met for flight times and skews due to trace mismatch and crosstalk.
On the motherboard the length of each data trace is either equal in length to the LAN_CLK trace or up
to 0.5 inches shorter than the LAN_CLK trace. (LAN_CLK should always be the longest motherboard
trace in each group.)