Design Guide

Platform Clock Routing Guidelines

248 Intel

855GM/855GME Chipset Platform Design Guide

12.2.4. PCI Clock Group

The PCI clocks are series terminated and routed point to point as on the Inter reference motherboard

between the CK408 and the PCI connectors, with a dedicated buffer for each slot. These clocks are

synchronous to the CLK33 clocks and are length tuned to compensate for the segment on the PCI

daughter card.

Figure 127. PCI Clock Group Topology

CK408 PCI Device

PCI

Connector

Trace on Card

Table 103. PCICLK Clock Group Routing Constraints

Parameter Definition

Class Name PCICLK

Class Type Individual Nets

Topology Series Terminated Point to Point

Reference Plane Ground Referenced

Single Ended Trace Impedance ( Zo ) 55 Ω+/-15%

Nominal Inner Layer Trace Width 4.0 mils

Nominal Outer Layer Trace Width 5.0 mils (pin escapes only)

Minimum Spacing (see exceptions below) 20 mils

Serpentine Spacing 20 mils

Maximum Via Count 4

Series Termination Resistor Value 33 Ω+/- 5 %

Trace Length Limits – L1 Up to 500 mils (breakout segment)

Trace Length Limits – L2 1.5” to 8.0”

Trace Length Limits – L3 2.5” (as per PCI specification)

Total Length Range – L1 + L2 + L3 CLK33 – 2.5” (for nominal matching)

Length Matching Required Yes (Pin to Pin)

Clock to Clock Length Matching +/- 2.0”

PCICLK to (CLK33 – 2.5”)

Breakout Region Exceptions

5 mil trace with 5 mil space on outers

4 mil trace with 4 mil space in inners

Maximum breakout length is 0.3”