Design Guide

Platform Clock Routing Guidelines
R
252 Intel
®
855GM/855GME Chipset Platform Design Guide
12.2.8. USBCLK Clock Group
The 48-MHz USBCLK is series terminated and routed point to point on the motherboard. This clock
operates independently and is not length tuned to any other clock.
Figure 131. USBCLK Clock Topology
L1
Rs
CK408
GMC
H
L2
Table 107. USBCLK Clock Routing Constraints
Parameter Definition
Class Name USBCLK
Class Type Individual Net
Topology Series Terminated Point to Point
Reference Plane Ground Referenced
Single Ended Trace Impedance ( Zo ) 55 Ω+/-15%
Nominal Inner Layer Trace Width 4.0 mils
Nominal Outer Layer Trace Width 5.0 mils (pin escapes only)
Minimum Spacing (see exceptions below) 20 mils
Maximum Via Count 4
Series Termination Resistor Value 33 Ω+/- 5 %
Trace Length Limits – L1 Up to 500 mils
Trace Length Limits – L2 3.0” to 12.0”
Total Length Range – L1 + L2 3.0” to 12.5”
Length Matching Required No
Breakout Exceptions 5 mil trace with 5 mil space on outers
4 mil trace with 4 mil space in inners
Maximum breakout length is 0.3”