Design Guide

Platform Clock Routing Guidelines

Intel

855GM/855GME Chipset Platform Design Guide 253

12.3. CK-408 Clock Updates for Intel Pentium M Processor

and Intel Celeron M Processor Platforms

To maximize the power savings on 855GM chipset based systems, additional control registers have been

added to the CK-408clock generator to allow option to tri-state the CPU[2:0] host clocks during

CPU_STOP# or PWRDWN assertion. The option to have CPU[2:0] driven (default) or tri-stated can be

programmed via the serial I

C bus interface to the CK-408 clock driver. If the tri-state feature on the

CPU[2:0] signals is chosen, it is recommended that the STP_CPU# signal from the Intel ICH4-M drive

the CK-408’s CPU_STOP# signal. Also, it is recommended that the ICH4-M’s DPSLP# signal be

connected to the DPSLP# pin of the processor and GMCH. Functionally, the ICH4-M’s STP_CPU# and

DPSLP# signals are equivalent. However, STP_CPU# is powered by the main I/O well (3.3 V) and is

sent to the CK-408 whereas DPSLP# is driven to the processor interface voltage (1.05 V).

12.4. CK-408 PWRDWN# Signal Connections

For systems that support the S1M state, the PWRDWN# input of the CK-408 clock chip is required to

be driven by both the SLP_S1# and SLP_S3# signals from the ICH4-M, i.e. the PWRDWN# pin of the

CK-408 should be driven by the output of the logical AND of the SLP_S1# and SLP_S3# signals. This

configuration best allows CPU[2:0] to be tri-stated during S1-M or lower (numerically higher) states.

For systems that do not support S1M but do support the S3 state, the PWRDWN# input of the CK-408

clock chip should be connected to the SLP_S3# output of the ICH4-M. It is not recommended that

PWRDWN# be pulled-up to the CK-408’s 3.3-V power supply if the S3 state is the second highest,

power consuming state supported by the platform (i.e. S1M and S2 not supported). The advantage of

using SLP_S3# rather than the 3.3-V supply to qualify PWRDWN# is that it reduces the likelihood of

the CK-408 clocks driving into unpowered components and potentially damaging the clock input

buffers. Also SLP_S3# can help reduce power consumption because it will be asserted before the 3.3-V

supply will be shut off, thus minimizing the amount of time that the clocks will be left toggling.