Design Guide

Intel 855GM/GME Chipset Based System Power Delivery Guidelines
R
Intel
®
855GM/855GME Chipset Platform Design Guide 257
13.3. Voltage Supply
13.3.1. Power Management States
Table 109. Power Management States on Intel Reference Board
Signal SLP_S
1#
SLP_S3# SLP_S4# SLP_S5# +V*ALW +V* +V*S Clocks
S0 (FULL ON) HIGH HIGH HIGH HIGH ON ON ON ON
S1M (POS) LOW HIGH HIGH HIGH ON ON ON LOW
S3 (STR) LOW LOW HIGH HIGH ON ON OFF OFF
S4 (STD) LOW LOW LOW HIGH ON OFF OFF OFF
S5 (Soft Off) LOW LOW LOW LOW ON OFF OFF OFF
13.3.2. Power Supply Rail Descriptions
Table 110. Power Supply Rail Descriptions on Intel Reference Board
Signal Names Voltage
(V)
Current
(A)
Tolerance Enable Description
SLP_S3# - HIGH GMCH, DDR
Termination
+V1_25 1.25 0.01 +/- 3.2%
SLP_S4# - HIGH DDR Reference (VREF)
+V1_5 1.5 0.03 +/- 5% SLP_S4# - HIGH LAN logic
CPU VCCA (Intel
Pentium M Processor
on 90 nm Process with
2 MB L2 Cache only)
+V1_5S 1.5 1.35 +/- 5% SLP_S3# - HIGH GMCHDVO-Core,
GMCH DLVDS, GMCH
DAC, GMCH ALVDS,
ICH4-M core, ICH4-M
VCCHL
+V1_5ALWAYS 1.5 0.1 +/- 5% +V3ALWAYS ICH4-M Resume
+V1_8S 1.8 0.6 +/- 5% SLP_S3# - HIGH CPU VCCA (Intel
Pentium M Processor
only)
+V1_2S for
855GM
+V1_35S for
855GME
1.2
1.35
1.8 +/- 5% SLP_S3# - HIGH GMCH Core, GMCH
HL, GMCH DPLL,
GMCH HPLL, GMCH
GPLL, GMCH VCCASM
+V2_5 2.5 8.12 +/- 5% SLP_S4# - HIGH GMCH DDR I/O, DDR
SO-DIMM, GMCH
TXLVDS
1