Design Guide

Intel 855GM/GME Chipset Based System Power Delivery Guidelines

Intel

855GM/855GME Chipset Platform Design Guide 259

Figure 133. GMCH Power-Up Sequence

CPURST#

RSTIN#

1ms min

1ms max

PWROK

GMCH PWR

Rails

13.4.3. ICH4-M Power Sequencing Requirements

The following figure describes the power-on timing sequence for ICH4-M. The VGATE input should be

connected to the processor voltage regulator PWRGD output. When both PWROK and VGATE are

asserted, it indicates that core power and system power are stable and PCIRST# will be de-asserted a

minimum of 1 ms later. It is the responsibility of the system designer to ensure that the power and timing

requirements for the processor and GMCH are met.

Please refer to Intel

82801DBM I/O Controller Hub 4-Mobile (ICH4-M) Datasheet for more details.