Design Guide

Intel 855GM/GME Chipset Based System Power Delivery Guidelines
R
260 Intel
®
855GM/855GME Chipset Platform Design Guide
Figure 134. ICH4-M Power-Up Sequence
VccSus (V*Always)
Running
SUSCLK
SLP_S3#
Vcc*, VccLAN,
(V_CPU_IO)
PWROK, VGATE,
LAN_PWROK
SUS_STAT#
PCIRST#
Frequency
Straps
STPCLK#, STP_CPU#, STP_PCI#
SLP_S1#, C3_STAT#
Strap Values
Normal Operation
Hub interface "CPU
Reset Complete”
M
essage
RSMRST#
T173
T176
T177
T178
T181
T181
T182
T184
T185
T186
G3 S3 S0 S0 stateG3 S5
System
State
S4
SLP_S4#
SLP_S5#
T183
T183a
T183b