Design Guide

Intel 855GM/GME Chipset Based System Power Delivery Guidelines
R
Intel
®
855GM/855GME Chipset Platform Design Guide 265
13.5.1. 855GM/GME Chipset GMCH Decoupling Guidelines
Decoupling in Table 15 is based on voltage regulator solution used on the customer reference board
design.
Table 113. GMCH Decoupling Recommendations
Pin Name Configuration F Qty TYPE Notes
VCC Connect to
VCC1_2S for
855GM
Connect to
VCC1_35S for
855GME
0.1 µF
10 µF
150 µF
4
1
2
XR7, 0603, 16 V, 10%
XR5, 1206, 6.3 V, 20%
SPC, E, 6.3 V, 20%
1 X 0.1 µF within 200 mils
3 X 0.1 µF on bottom side
VTTLF Connect to
VCCP
0.1 µF
10 µF
150 µF
2
1
1
XR7, 0603, 16 V, 10%
XR5, 1206, 6.3 V, 20%
SPC, E, 6.3 V, 20%
2 X 0.1 µF on bottom side
VTTHF Connect to caps
directly
0.1 µF 5 XR7, 0603, 16 V, 10%
VCCHL Connect to
VCC1_2S for
855GM
Connect to
VCC1_35S for
855GME
0.1 µF
10 µF
2
1
XR7, 0603, 16 V, 10%
XR5, 1206, 6.3 V, 20%
1 X 0.1 µF within 200 mils
1 X 0.1 µF on bottom side
VCCSM Connect to
VCCSus2_5
0.1 µF
150 µF
11
2
XR7, 0603, 16 V, 10%
TANT, D, 10 V, 20%
See section 1.5.2.1
VCCDVO Connect to
VCC1_5S
0.1 µF
10 µF
150 µF
2
1
1
XR7, 0603, 16 V, 10%
XR5, 1206, 6.3 V, 20%
SPC, E, 6.3 V, 20%
1 X 0.1 µF within 200 mils
1 X 0.1 µF on bottom side
VCCDLVDS Connect to
VCC1_5S
0.1 µF
22 µF
47 µF
1
1
1
XR7, 0603, 16 V, 10%
TANT, B, 10 V, 20%
TANT, D, 10 V, 20%
1 X 0.1 µF within 200 mils
VCCTXLVDS
1
Connect to
VCCSus2_5
0.1 µF
22 µf
47 µF
3
1
1
XR7, 0603, 16 V, 10%
TANT, B, 10 V, 20%
TANT, D, 10 V, 20%
1 X 0.1 µF within 200 mils
2 X 0.1 µF on bottom side
VCCGPIO Connect to
Vcc3_3S
0.1 µF
10 µF
1
1
XR7, 0603, 16 V, 10%
XR5, 1206, 6.3 V, 20%
SMVREF 0.1 µF 1 XR7, 0603, 16 V, 10% 1 X 0.1 µF on bottom side
NOTE: Not required when using 855GME platform design with external graphics only.