Design Guide

Reserved, NC, and Test Signals

Intel

855GM/855GME Chipset Platform Design Guide 279

15. Reserved, NC, and Test Signals

The Intel Pentium M processor, Intel Pentium M Processor on 90 nm Process with 2 MB L2 Cache,

855GM/GME chipset GMCH may have signals listed as “RSVD”, “NC”, or other name whose

functionality is Intel reserved. The following section contains recommendations on how these Intel

reserved signals on the processor or GMCH should be handled.

15.1. Intel Pentium M Processor and Intel Celeron M

Processor RSVD Signals

The Intel Pentium M processor and Intel Celeron M processor each have a total of three TEST, and eight

RSVD signals that are Intel reserved in the pin-map. All other RSVD signals are to be left unconnected

but should have access to open routing channels for possible future use. The location of the Intel

reserved signals in the processor pin-map is listed in Table 116.

Table 116. Processor RSVD and TEST Signal Pin-Map Locations

Signal Name Ball Name

RSVD (LAI usage) AF7

RSVD (key) A1

RSVD B2

RSVD C3

RSVD C14

RSVD (PSI#) E1

RSVD (former GTLREF1) E26

RSVD (former GTLREF2) G1

RSVD (former GTLREF3) AC1

TEST1 C5

TEST2 F23

TEST3 C16

15.2. Intel Pentium M Processor on 90 nm Process with 2

MB L2 Cache Processor RSVD Signals

The Intel Pentium M Processor on 90 nm Process with 2 MB L2 Cache Processor is pin compatible

with the Intel Pentium M processor. Pins C14 and C16 are defined as BSEL1 and BSEL0 respectively

for Intel Pentium M Processor on 90 nm Process with 2 MB L2 Cache processor for future platform

functionality. They should be left as NC on 855GM/GME chipset based systems.