Design Guide

Platform Design Checklist
R
Intel
®
855GM/855GME Chipset Platform Design Guide 291
16.6. Intel 855GM/855GME Checklist
16.6.1. System Memory
16.6.1.1. GMCH System Memory Interface
Pin Name System
Pull-up/Pull-down
Series
Resistor
Notes
9
RCVENIN# This signal should be routed to a via next to ball and left
as a NC (No Connect).
RCVENOUT# This signal should be routed to via next to ball and left as
a NC (No Connect).
SBA[1:0], SCAS#,
SRAS#, SWE#
56
Ω pull-up to Vcc1_25 10 Ω
Three topologies available for routing these signals.
SCKE[3:0],
SCS#[3:0]
56
Ω pull-up to Vcc1_25
SDQ[63:0],
SDM[7:0],
SDQS[7:0]
56
Ω pull-up to Vcc1_25 10 Ω
SDQ[71:64],
SDM8, SDQS8
56
Ω pull-up to Vcc1_25 10 Ω
If ECC support is not implemented, SDQ[71:64], SDM8,
and SDQS8 should be left as NC. For ECC support,
these signals connect to SO-DIMMs.
SMA[12:6,3,0]
56
Ω pull-up to Vcc1_25 10 Ω
Three topologies available for routing these signals.
SMA[5,4,2,1]
SMAB[5,4,2,1]
56
Ω pull-up to Vcc1_25
Use SMA[5,4,2,1] for one SO-DIMM connector; use
SMAB[5,4,2,1] for the other SO-DIMM connector.
SCK0, SCK0#
SCK1, SCK1#
These clock signals connect to SO-DIMM 0.
SCK2, SCK2# If ECC supported is not implemented, these clock signals
should be left as NC. For ECC support, these signals
connect to SO-DIMM 0.
SCK3, SCK3#
SCK4, SCK4#
These clock signals connect to SO-DIMM 1.
SCK5, SCK5# If ECC supported is not implemented, these clock signals
should be left as NC. For ECC support, these signals
connect to SO-DIMM 1.
SMVREF
10 kΩ 1% pull-up to VccSus2_5
10 k
Ω 1% pull-down to gnd
Signal voltage level = VccSus2_5/ 2. Note that a buffer
is used to provide the necessary current and reference
voltage to SMVREF. Place a 0.1uF cap by GMCH.
See Figure 152.
SMVSWINGL
604 Ω 1% pull-up to VccSus2_5
150
Ω 1% pull-down to gnd
Signal voltage level = 1/5 * VccSus2_5.
Need 0.1 µF cap at pin.
This signal may be optionally connected to Vcc2_5 and
powered off in S3.
SMVSWINGH
150 Ω 1% pull-up to VccSus2_5
604
Ω 1% pull-down to gnd
Signal voltage level = 4/5 * VccSus2_5.
Need 0.1 µF cap at pin.
This signal may be optionally connected to Vcc2_5 and
powered off in S3.