Design Guide

Platform Design Checklist
R
298 Intel
®
855GM/855GME Chipset Platform Design Guide
16.6.5. Miscellaneous
Pin Name System
Pull-up/Pull-down
Notes
9
EXTTS
10 k
Ω 1% pull-up to Vcc3_3
DPWR# (pin
AA22)
Connect to the processor.
LCLKCTLB Leave as NC if not used.
LCLKCTLA Leave as NC if not used.
GST[2:0]
Leave as NC or 1 k
Ω pull-up to Vcc1_5
These pins have internal pull-down.