Design Guide

R
Intel® 855GM/855GME Chipset Platform Design Guide 3
Contents
1. Introduction .................................................................................................................................21
1.1. Referenced Documents .................................................................................................23
2. System Overview........................................................................................................................25
2.1. Platform Component Features.......................................................................................25
2.2. Intel 855GM Platform Component Features..................................................................26
2.2.1. Intel
®
Pentium
®
M Processor and Intel Celeron M Processor .......................26
2.2.2. Intel
®
855GM Chipset Graphics Memory Controller Hub (GMCH) ................27
2.2.2.1. Intel Pentium M Processor and Intel Celeron M Processor FSB
Support............................................................................................27
2.2.2.2. Integrated System Memory DRAM Controller ................................27
2.2.2.3. Internal Graphics Controller ............................................................27
2.2.2.4. Package/Power ...............................................................................28
2.2.3. Intel
®
82801DBM I/O Controller Hub 4-Mobile (ICH4-M)...............................28
2.2.4. Intel
®
Pro/Wireless Network Connection........................................................29
2.3. Intel 855GME Platform Component Features ...............................................................30
2.3.1. Intel Pentium
®
M Processor on 90 nm Process with 2 MB L2 Cache ...........30
2.3.2. Intel 855GME Chipset Graphics Memory Controller Hub (GMCH) ...............31
2.3.2.1. Accelerated Graphics Port (AGP) Interface....................................31
3. General Design Considerations .................................................................................................33
3.1. Nominal Board Stack-Up ...............................................................................................33
3.2. Alternate Stack Ups .......................................................................................................34
4. Intel Pentium M/Celeron M Front Side Bus Design Guidelines..................................................37
4.1. Intel Pentium M Processor / Intel Celeron M FSB Design Recommendations .............37
4.1.1. Recommended Stack-up Routing and Spacing Assumptions .......................37
4.1.1.1. Trace Space to Trace – Reference Plane Separation Ratio ..........37
4.1.1.2. Trace Space to Trace Width Ratio..................................................38
4.1.2. Common Clock Signals..................................................................................38
4.1.2.1. Processor Common Clock Signal Package Length Compensation39
4.1.3. Source Synchronous Signals General Routing Guidelines ...........................40
4.1.3.1. Source Synchronous Signal Length Matching Constraints ............43
4.1.3.2. Package Length Compensation......................................................43
4.1.3.3. Source Synchronous – Data Group................................................44
4.1.3.4. Source Synchronous – Address Group ..........................................45
4.1.3.5. Intel Pentium M / Intel Celeron M Processor and Intel
855GM/GME Chipset GMCH PSB Signal Package Lengths .........46
4.1.4. Asynchronous Signals....................................................................................49
4.1.4.1. Topology 1A: Open Drain (OD) Signals Driven by the Processor –
IERR#..............................................................................................50
4.1.4.2. Topology 1B: Open Drain (OD) Signals Driven by the Processor –
FERR# and THERMTRIP# .............................................................50
4.1.4.3. Topology 1C: Open Drain (OD) Signals Driven by the Processor –
PROCHOT# ....................................................................................51
4.1.4.4. Topology 2A: Open Drain (OD) Signals Driven by ICH4-M –
PWRGOOD.....................................................................................52
4.1.4.5. Topology 2B: CMOS Signals Driven by ICH4-M – DPSLP# ..........53
4.1.4.6. Topology 2C: CMOS Signals Driven by ICH4-M – LINT0/INTR,
LINT1/NMI, A20M#, IGNNE#, SLP#, SMI#, and STPCLK# ...........53
4.1.4.7. Topology 3: CMOS Signals Driven by ICH4-M to CPU and FWH –
INIT#................................................................................................54