Design Guide

Platform Design Checklist
R
Intel
®
855GM/855GME Chipset Platform Design Guide 305
16.7.6. ICH4-M Power Management Interface
Pin Name System
Pull-up/Pull-down
Notes
9
PM_DPRSLPVR Signal has integrated pull-down in ICH4-M.
PM_SLP_S1#/GPIO19
PM_SLP_S3#,
PM_SLP_S4#,
PM_SLP_S5#
Signals driven by ICH4-M.
PM_BATLOW#
10 k
Ω pull-up to V3ALWAYS
IF NOT USED
Pull up is not required if it is used. However, signal must
not float if it is NOT being used
PM_CLKRUN#
10 k
Ω pull-up to Vcc3_3
PM_PWRBTN#
Has integrated pull-up of 18 k
Ω – 42 kΩ.
PM_PWROK Weak pull-down to gnd RTC well input requires pull-down to reduce leakage from
coin cell battery in G3. Input must not float in G3.
This signal should be connected to power monitoring logic
and should go high no sooner than 10 ms after both
Vcc3_3 and Vcc1_5 have reached their nominal voltages.
CRB uses 100 K
Ω pull-down.
PM_RI#
8.2 k
Ω-10 kΩ pull-up to
V3ALWAYS
If this signal is enabled as a wake event, it needs to be
powered during a power loss event. If this signal goes low
(active), when power returns the RI_STS bit will be set
and the system will interpret that as a wake event.
PM_RSMRST# Weak pull-down to gnd RSMRST# is a RTC well input and requires pull-down to
reduce leakage from coin cell battery in G3. Input must not
float in G3.
This signal should be connected to power monitoring logic
and should go high no sooner than 10 ms after both
Vcc3_3 and Vcc1_5 have reached their nominal voltages.
CRB uses 100 K
Ω pull-down.
Timing Requirement: See LAN_RST#.
PM_THRM#
8.2 k
Ω Pull-up to Vcc3_3
If TEMP SENSOR not sued
External pull-up not required if connecting to temperature
sensor.
PM_SYSRST#
10 k
Ω pull-up to V3ALWAYS
if not actively driven.
This signal to ICH4-M should not float. It needs to be at
valid level all the time.
16.7.7. FWH/LPC Interface
Pin Name System
Pull-up/Pull-down
Notes
9
LPC_AD[3:0]
No extra pull-ups required. Connect straight to FWH/LPC.